IDT77V126L200TFI IDT, Integrated Device Technology Inc, IDT77V126L200TFI Datasheet
IDT77V126L200TFI
Specifications of IDT77V126L200TFI
Related parts for IDT77V126L200TFI
IDT77V126L200TFI Summary of contents
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Features ! Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions of the Physical Layer ! Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5 specifications for 25.6 Mbps physical interface ! Operates at 25.6, 51.2, 102.4, 204.8 ...
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IDT77V126L200 77V126L200 Overview The 77V126L200 is a physical layer interface chip for up to 200Mbps data rate ATM network communications as defined by ATM Forum docu- ment af-phy-040.000 and ITU-T I.432.5. The physical layer is divided into a Physical Media ...
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IDT77V126L200 RXREF TXREF TXLED TXDATA0 TXDATA1 TXDATA2 TXDATA3 TXDATA4 TXDATA5 TXDATA6 TXDATA7 TXPARITY TXEN TXSOC VDD TXCLAV Pin 1 Index 77V126 ...
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IDT77V126L200 Signal Descriptions Signal Name Pin Number I/O Signal Description RXD+, RXD- 58 Positive and negative receive differential input pair. TXD+, TXD- 62, 61 Out Positive and negative transmit differential output pair. Signal Name Pin Number I/O Signal ...
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IDT77V126L200 Signal Name Pin Number I/O Signal Description INT 34 Out Interrupt. INT is an open-drain output, driven low to indicate an interrupt. Once low, INT remains low until the interrupt status in the appropriate interrupt Status Register is read. ...
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IDT77V126L200 Functional Description Transmission Convergence (TC) Sub Layer Introduction The TC sub layer defines the line coding, scrambling, data framing and synchronization. Under control of a switch interface or Segmenta- tion and Reassembly (SAR) unit, the 25.6Mbps ATM PHY accepts ...
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IDT77V126L200 Transmit Block Diagram 3 Cells PHY-ATM UTOPIA Interface HEC Gen. & Start of Cell 4 Scrambler Interface Control, 4 Insertion Scramble Nibble Pseudo Random PRNG Nibble Generator 32MHz 64MHz Line Rate Clock Clock Input Figure 2 TC Transmit Block ...
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IDT77V126L200 This encode/decode implementation has several very desirable properties. Among them is the fact that the output data bits can be represented by a set of relatively simple symbols; ! Run length is limited to < Disparity never ...
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IDT77V126L200 There is a single 8-bit data bus in the transmit (ATM-to-PHY) direction, and a single 8-bit data bus in the receive (PHY-to-ATM) direction. In addition to the data bus, each direction also includes a single optional parity bit and ...
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IDT77V126L200 The Utopia signals are summarized below: TXDATA[7:0] ATM to PHY TXPARITY ATM to PHY TXSOC ATM to PHY TXEN ATM to PHY TXCLAV PHY to ATM TXCLK ATM to PHY RXDATA[7:0] PHY to ATM RXPARITY PHY to ATM RXSOC ...
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IDT77V126L200 TXCLK TXCLAV TXEN TXDATA[7:0], P46 TXPARITY TXSOC Figure 5 Utopia Transmit Handshake - Back to Back Cells and TXEN Suspended Transmission TXCLK TXCLAV TXEN TXDATA[7:0], P42 P43 TXPARITY TXSOC Figure 6 Utopia Transmit Handshake - TXEN Suspended Transmission and ...
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IDT77V126L200 RXCLK RXCLAV RXEN RXDATA[7:0], P47 P48 RXPARITY RXSOC RXCLK RXCLAV RXEN High-Z RXDATA[7:0], P42 RXPARITY High-Z RXSOC RXCLK RXCLAV RXEN High-Z RXDATA[7:0], RXPARITY High-Z RXSOC Figure 10 Utopia Receive Handshake - RXCLAV Suspended Transfer (Octet Mode Only) High-Z H1 ...
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IDT77V126L200 Control and Status Interface Utility Bus The Utility Bus is a byte-wide interface that provides access to the registers within the IDT77V126L200. These registers are used to select desired operating characteristics and functions, and to communicate status to external ...
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IDT77V126L200 Loopback There are two loopback modes supported by the 77V126L200. The loopback mode is controlled via bits 1 and 0 of the Diagnostic Control Register: Normal Mode Figure 12 shows normal operating conditions: data to be transmitted is transferred ...
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IDT77V126L200 Counters Several condition counters are provided to assist external systems (e.g. software drivers) in evaluating communications conditions anticipated that these counters will be polled from time to time (user selectable) to evaluate performance. ! Symbol Error Counters ...
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IDT77V126L200 OSC Line Card 1 Normal Mode Loop Timing Jitter Specification Line Rate Data Rate Mbps 32 64 128 256 The waveforms below show some of the measurements taken with the set-up in Figure 15. Using the ...
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IDT77V126L200 Jitter at 25.6Mbps at point 4 with respect to point 1 Jitter at 51.2Mbps at point 4 with respect to point 1 Jitter at 25.6Mbps at point 5 with respect to point 1 Jitter at 51.2Mbps at point 5 ...
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IDT77V126L200 Jitter at 102.4Mbps at point 4 with respect to point 1 Jitter at 256Mbps at point 4 with respect to point 1 From the above measurements taken, the amount of jitter being added at each TX point is not ...
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IDT77V126L200 PHY to Magnetics Interface Magnetics AGND AVDD ...
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IDT77V126L200 Status and Control Register List Master Control Register Address: 0x00 Bit Type Initial State 7 R/W Reserved 6 R discard Discard Receive Error Cells On receipt of any cell with an error (e.g. short cell, invalid command ...
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IDT77V126L200 5 sticky 0 HEC error cell received Set when a HEC error is detected on received cell. 4 sticky 0 "Short Cell" Received Interrupt signal which flags received cells with fewer than 53 bytes. This condition is detected when ...
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IDT77V126L200 LED Driver and HEC Status/Control Register Address: 0x03 Bit Type Initial State Reserved 6 R enable Disable Receive HEC Checking (HEC Enable) checking When not set, the HEC is calculated on first 4 bytes ...
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IDT77V126L200 Interrupt Mask Register Address: 0x07 Bit Type Initial State R interrupt enabled 4 R interrupt enabled 3 R interrupt enabled 2 R interrupt enabled 1 R/W ...
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IDT77V126L200 Absolute Maximum Ratings Symbol V TERM T BIAS T STG I OUT Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of ...
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IDT77V126L200 DC Electrical Characteristics (All Pins except TX+/- and RX+/-) Symbol I Input Leakage Current (as input) Leakage Current Output Logic "1" Voltage OH1 2 V Output Logic "1" Voltage OH2 3 V Output ...
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IDT77V126L200 UTOPIA Level 1 Bus Timing Parameters Symbol t31 TXCLK Frequency t32 TXCLK Duty Cycle (% of t31) t33 TXDATA[7:0], TXPARITY Setup Time to TXCLK t34 TXDATA[7:0], TXPARITY Hold Time to TXCLK t35 TXSOC, TXEN[3:0] Setup Time to TXCLK t36 ...
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IDT77V126L200 Utility Bus Read Cycle Name Min Max Unit Tas 10 — MHz Address setup to ALE Tcsrd 0 — % Chip select to read enable Tah 5 — ns Address hold to ALE Tapw 10 — ns ALE min ...
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IDT77V126L200 OSC, TXREF and Reset Timing Symbol Tcyc OSC cycle period (25.6 Mbps) (51.2 Mbps) Tckh OSC high time Tckl OSC low time Tcc OSC cycle to cycle period variation Ttrh TXREF High Time Ttrl TXREF Low Time Trspw Minimum ...
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IDT77V126L200 Package Dimensions 4.4458 ' D 5.5125 ' SYMBOL ccc ddd Dimensions are in millimeters PSC-4046 is a more comprehensive package outline drawing which is available ...
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IDT77V126L200 Ordering Information IDT NNNNN A Device Type Power Revision History September 20, 2001: Initial publication. December 9, 2004: Removed Commerical Temperature Range from Datasheet and updated to current template. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 NNN ...