ICS87421AMIT IDT, Integrated Device Technology Inc, ICS87421AMIT Datasheet - Page 8

• Manufacturer Part Number: ICS87421AMIT
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Dividerr

Specifications of ICS87421AMIT

• Number Of Clock Inputs: 1
• Mode Of Operation: Differential
• Output Logic Level: LVDS
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: SOIC N
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Not Compliant

F
IDT
F
D
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
V
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
F
IGURE
PP
IGURE
IGURE
ICS87421I
÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR
IFFERENTIAL
™
and V
2.5V
/ ICS
HCSL
3.3V
3C. H
3A. H
3E. H
*Optional – R3 and R4 can be 0
™
1.8V
CMR
LVPECL
LVDS CLOCK GENERATOR
input requirements. Figures 3A to 3F show interface
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
D
D
H
D
*R3
*R4
I
RIVEN BY A
I
RIVEN BY AN
I
P
I
RIVEN BY A
P
P
P
C
ER
ER
ER
ER
Zo = 50 Ohm
Zo = 50 Ohm
LOCK
C
33
33
Zo = 50 Ohm
Zo = 50 Ohm
C
C
C
LOCK
LOCK
LOCK
LOCK
I
NPUT
3.3V LVPECL D
Zo = 50
Zo = 50
S CLK/nCLK I
3.3V HCSL D
S CLK/nCLK I
S LVHSTL D
S CLK/nCLK I
IDT O
R1
50
3.3V
R3
125
I
R1
84
NTERFACE
R1
50
PEN
R2
50
SWING
R4
125
R2
84
E
MITTER
RIVER
and V
CLK
nCLK
R2
50
RIVER
NPUT
NPUT
CLK
nCLK
NPUT
3.3V
RIVER
3.3V
CLK
nCLK
HiPerClockS
Input
OH
HiPerClockS
Input
3.3V
must meet the
HiPerClockS
Input
8
F
component to confirm the driver termination requirements. For
example in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
F
F
IGURE
IGURE
IGURE
2.5V
3.3V
3.3V
SSTL
3D. H
3B. H
LVDS_Driv er
3F. H
LVPECL
D
D
D
I
RIVEN BY A
I
RIVEN BY A
I
RIVEN BY A
P
P
P
Zo = 50 Ohm
Zo = 50 Ohm
ER
ER
ER
Zo = 60
Zo = 60
C
C
C
LOCK
LOCK
LOCK
Zo = 50 Ohm
Zo = 50 Ohm
3.3V LVDS D
3.3V LVPECL D
S CLK/nCLK I
2.5V SSTL D
S CLK/nCLK I
S CLK/nCLK I
ICS87421AMI REV. A OCTOBER 3, 2007
R1
50
R3
50
R3
120
2.5V
R1
120
R2
50
R1
100
R4
120
R2
120
CLK
nCLK
3.3V
RIVER
RIVER
NPUT
NPUT
NPUT
HiPerClockS
RIVER
Input
CLK
nCLK
CLK
nCLK
3.3V
3.3V
HiPerClockS
Receiv er