ICS83940DY IDT, Integrated Device Technology Inc, ICS83940DY Datasheet - Page 11

• Manufacturer Part Number: ICS83940DY
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of ICS83940DY

• Number Of Clock Inputs: 2
• Output Frequency: 250MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: LQFP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Not Compliant

IDT™ / ICS™ LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
ICS83940D
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
83940DY
LVPECL C
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V
and V
examples for the HiPerClockS PCLK/nPCLK input driven by
the most common driver types. The input interfaces suggested
F
F
F
IGURE
IGURE
IGURE
CMR
2A. H
2E. H
2C. H
3.3V
3.3V
input requirements. Figures 2A to 2F show interface
2.5V
LVPECL
CML
BY AN
BY AN
BY A
SSTL
LOCK
I
I
I
P
P
P
Integrated
Circuit
Systems, Inc.
ER
ER
ER
3.3V LVPECL D
O
SSTL D
Zo = 50 Ohm
Zo = 50 Ohm
C
C
C
I
Zo = 50 Ohm
Zo = 50 Ohm
PEN
Zo = 60 Ohm
Zo = 60 Ohm
LOCK
NPUT
LOCK
LOCK
C
S PCLK/nPCLK I
S PCLK/nPCLK I
S PCLK/nPCLK I
OLLECTOR
SWING
I
RIVER
NTERFACE
3.3V
R1
50
2.5V
R3
120
and V
3.3V
R3
125
R1
120
R1
84
RIVER
R2
50
R4
120
CML D
R2
120
R4
125
OH
R2
84
PCLK
nPCLK
must meet the V
3.3V
PCLK
nPCLK
www.icst.com/products/hiperclocks.html
PCLK
nPCLK
3.3V
RIVER
HiPerClockS
PCLK/nPCLK
NPUT
NPUT
NPUT
3.3V
HiPerClockS
PCLK/nPCLK
Input
HiPerClockS
D
D
D
RIVEN
RIVEN
RIVEN
LVPECL-
PP
11
11
here are examples only. If the driver is from another vendor,
use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver ter-
mination requirements.
F
F
F
IGURE
IGURE
IGURE
3.3V
3.3V
TO
3.3V
2B. H
3.3V LVPECL
2D. H
2F.
LVDS
-LVCMOS / LVTTL F
CML Built-In Pullup
R5
100 - 200
BY A
BY A
H
BY A
I
I
Zo = 50 Ohm
Zo = 50 Ohm
I
P
P
P
ER
ER
ER
B
3.3V LVPECL D
3.3V LVDS D
R6
100 - 200
C
C
UILT
C
Zo = 50 Ohm
Zo = 50 Ohm
LOCK
LOCK
LOCK
R5
100
-I
N
Zo = 50 Ohm
Zo = 50 Ohm
S PCLK/nPCLK I
S PCLK/nPCLK I
S PCLK/nPCLK I
P
ULLUP
C1
C2
L
C1
C2
RIVER
OW
CML D
3.3V
R3
84
RIVER WITH
R1
125
R1
100
3.3V
R3
1K
R1
1K
S
R4
84
ANOUT
R2
125
KEW
R4
1K
PCLK
nPCLK
RIVER
R2
1K
3.3V
REV. B JUNE 15, 2004
NPUT
NPUT
NPUT
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
PCLK
nPCLK
AC C
, 1-
3.3V
3.3V
B
D
D
D
HiPerClockS
PCL K/n PC LK
HiPerClockS
PCLK/nPCLK
TO
UFFER
RIVEN
RIVEN
RIVEN
OUPLE
-18
ICS83940D
TSD