ICS854057AG IDT, Integrated Device Technology Inc, ICS854057AG Datasheet - Page 5

• Manufacturer Part Number: ICS854057AG
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Multiplexerr

Specifications of ICS854057AG

• Number Of Clock Inputs: 4/2
• Mode Of Operation: Differential
• Output Frequency: >2000MHz
• Output Logic Level: LVDS
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 2.625V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: CML/LVDS/LVPECL/SSTL
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Not Compliant

The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
854057AG
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
100
Integrated
Circuit
Systems, Inc.
1k
10k
O
www.icst.com/products/hiperclocks.html
FFSET
A
DDITIVE
F
ROM
100k
C
ARRIER
P
HASE
5
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
F
REQUENCY
1M
J
4:1
ITTER
Additive Phase Jitter
OR
WITH
(H
2:1 LVDS C
Z
)
10M
I
NTERNAL
(12kHz to 20MHz)
100M
@ 622.08MHz
= 66fs typical
I
LOCK
NPUT
ICS854057
REV. A OCTOBER 29, 2008
M
T
ERMINATION
ULTIPLEXER
500M