ICS854057AG IDT, Integrated Device Technology Inc, ICS854057AG Datasheet

ICS854057AG

Manufacturer Part Number
ICS854057AG
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Multiplexerr
Datasheet

Specifications of ICS854057AG

Number Of Clock Inputs
4/2
Mode Of Operation
Differential
Output Frequency
>2000MHz
Output Logic Level
LVDS
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (typ)
2.5V
Operating Supply Voltage (max)
2.625V
Package Type
TSSOP
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Signal Type
CML/LVDS/LVPECL/SSTL
Mounting
Surface Mount
Pin Count
20
Lead Free Status / RoHS Status
Not Compliant
B
G
tial input levels. Internal termination is provided on each dif-
ferential input pair. The ICS854057 operates using a 2.5V sup-
ply voltage. The fully differential architecture and low propa-
gation delay make it ideal for use in high speed multiplexing
applications. The select pins have internal pulldown resistors.
Leaving one input unconnected (pulled to logic low by the in-
ternal resistor) will transform the device into a 2:1 multiplexer.
The SEL1 pin is the most significant bit and the binary num-
ber applied to the select pins will select the same numbered
data input (i.e., 00 selects PCLK0, nPCLK0).
854057AG
HiPerClockS™
ICS
LOCK
ENERAL
nPCLK0
nPCLK1
nPCLK2
nPCLK3
PCLK0
PCLK1
PCLK2
PCLK3
SEL1
SEL0
VT0
VT1
VT2
VT3
D
The ICS854057 is a 4:1 or 2:1 LVDS Clock Mul-
tiplexer which can operate up to 2GHz and is a
member of the HiPerClockS™ family of High Per-
formance Clock Solutions from ICS. The PCLK,
nPCLK pairs can accept most standard differen-
50
50
50
50
Pulldown
Pulldown
IAGRAM
Integrated
Circuit
Systems, Inc.
D
50
50
50
50
ESCRIPTION
00
01
10
11
www.icst.com/products/hiperclocks.html
Q
nQ
1
F
P
High speed differential multiplexer. The device can be
configured as either a 4:1 or 2:1 multiplexer
Single LVDS output
4 selectable PCLK, nPCLK inputs with internal termination
PCLK, nPCLK pairs can accept the following differential
input levels: LVPECL, LVDS, CML, SSTL
Output frequency: >2GHz
Part-to-part skew: 200ps (maximum)
Propagation delay: 800ps (maximum)
Additive phase jitter, RMS: 66fs (typical)
2.5V operating supply
-40°C to 85°C ambient operating temperature
Available in both, Standard and RoHS/Lead-Free compliant
packages
EATURES
IN
4:1
A
4.40mm x 6.50mm x 0.925mm body package
SSIGNMENT
OR
WITH
2:1 LVDS C
nPCLK0
nPCLK1
PCLK0
PCLK1
SEL1
SEL0
GND
VT0
VT1
V
I
DD
20-Lead TSSOP
NTERNAL
ICS854057
G Package
Top View
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
I
LOCK
NPUT
V
PCLK3
VT3
nPCLK3
Q
nQ
PCLK2
VT2
nPCLK2
GND
ICS854057
DD
REV. A OCTOBER 29, 2008
M
T
ERMINATION
ULTIPLEXER

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ICS854057AG Summary of contents

Page 1

Integrated Circuit Systems, Inc ENERAL ESCRIPTION The ICS854057 is a 4:1 or 2:1 LVDS Clock Mul- ICS tiplexer which can operate up to 2GHz and is a HiPerClockS™ member of the HiPerClockS™ family of High Per- formance Clock ...

Page 2

Integrated Circuit Systems, Inc ABLE IN ESCRIPTIONS ...

Page 3

Integrated Circuit Systems, Inc BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs Continuous Current 10mA Surge Current 15mA Package Thermal Impedance, JA Storage Temperature, T -65°C to 150°C STG ...

Page 4

Integrated Circuit Systems, Inc. T 4D. LVDS DC C ABLE HARACTERISTICS ...

Page 5

Integrated Circuit Systems, Inc. The spectral purity in a band at a specific offset from the funda- mental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise ...

Page 6

Integrated Circuit Systems, Inc. P ARAMETER V DD 2.5V±5% POWER SUPPLY LVDS + - Float GND 2. UTPUT OAD EST IRCUIT nPCLKx PCLKx nPCLKy PCLKy PD2 t PD1 tsk(i) tsk( ...

Page 7

Integrated Circuit Systems, Inc. 80% Clock 20% Outputs UTPUT ISE ALL IME V DD LVDS DC Input ➤ FFSET OLTAGE ETUP 854057AG 4 80% LVDS DC Input V ...

Page 8

Integrated Circuit Systems, Inc. 2.5V LVDS D T RIVER ERMINATION Figure 1 shows a typical termination for LVDS driver in charac- teristic impedance of 100 differential (50 2.5V LVDS_Driv er 2. IFFERENTIAL NPUT WITH To prevent oscillation ...

Page 9

Integrated Circuit Systems, Inc. LVPECL NPUT WITH UILT N The PCLK /nPCLK with built-in 50 LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both V and V must meet the V SWING OH input ...

Page 10

Integrated Circuit Systems, Inc ECOMMENDATIONS FOR NUSED I : NPUTS PCLK/nPCLK I : NPUT For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but ...

Page 11

Integrated Circuit Systems, Inc ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in ...

Page 12

Integrated Circuit Systems, Inc ACKAGE UTLINE UFFIX FOR T ABLE Reference Document: JEDEC Publication 95, MO-153 854057AG 4:1 OR TSSOP EAD ACKAGE IMENSIONS ...

Page 13

Integrated Circuit Systems, Inc ABLE RDERING NFORMATION ...

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