FW82371EB Intel, FW82371EB Datasheet - Page 37

• Manufacturer Part Number: FW82371EB
• Manufacturer: Intel

Specifications of FW82371EB

• Lead Free Status / RoHS Status: Not Compliant

Specification Update
R
7.3.3 SMBHSTCNT—SMBUS HOST CONTROL REGISTER (IO)
I/O Address:
Default Value:
Attribute:
The control register is used to enable SMBus controller host interface functions. Reads to this register
clears the host interface’s index pointer to the block data storage array.
In the PIIX4 datasheet, Pages 266-267, Section 11.5.4.1, SMBus Host Interface, paragraph 2 should be
modified as follows:
11.5.4.1 SMBus Host Interface
A SMBus Host Controller is used to send commands to various SMBus devices. The PIIX4 SMBus
controller implements a full host controller implementation. The PIIX4 SMBus controller supports seven
command protocols of the SMBus interface (see System Management Bus Specification, Revision 1.0):
Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Block Read, and Block
Write.
To execute a SMBus host transaction, the type of transfer protocol, the address of SMBus device, the
device specific command, the data, and any control bits are first setup. Then the START bit is set, which
causes the host controller to execute the transaction. When the transaction is completed, PIIX4 generates
an interrupt, if enabled. The interrupt can be selected between IRQ9OUT or SMI#. The system software
can wait for an interrupt to signal completion or it can monitor the SMBus Interrupt/Host Completion
status bit. An interrupt is also signaled if an error occurred during the transaction or if the transaction was
terminated by software setting the KILL bit. The SMBHSTCNT, SMBHSTCMD, SMBHSTADD,
SMBHSTDAT0, SMBHSTDAT1, and SMBBLKDAT registers should not be accessed after setting the
START bit while the HOST_BUSY bit is active until completion of the transaction as indicated by the
SMBus Interrupt/Host Completion status bit going active.
Bit
4:2
7
6
5
1
0
Reserved.
Start (START)—R/W. 1=Start execution. Writing a 1 to this bit initiates the SMBus controller host
interface to execute the command programmed in the SMB_CMD_PORT field. All necessary
registers should be setup prior to writing a 1 to this bit position. 0=Writing a 0 has no effect. This
bit always reads 0. The HOST_BUSY bit can be used to identify when the SMBus host controller
has finished executing the command.
Reserved.
SMBus Command Protocol (SMB_CMD_PROT)—R/W. Selects the type of command the
SMBus controller host interface will execute. Reads or writes are determined by bit 0 of
SMBHSTADD register. This field is decoded as follows:
Bits[4:2]
Kill (KILL)—R/W. 1=Stop the current in process SMBus controller host transaction. This sets the
FAILED status bit and asserts the interrupt selected by the SMB_INTRSEL field. 0=Allows the
SMBus controller host interface to function normally.
Interrupt Enable (INTEREN)—R/W. 1= Enable the generation of interrupts (IRQ9OUT) or SMI (as
defined in the table listed in section 7.1.28., SMBUS HOST CONFIGURATION REGISTER
(Function 3), bit [3:1], SMBus Interrupt Select) on the completion of the current host transaction.
0=Disable.
000
001
010
011
Base + (02h)
00h
Read/Write
Protocol
Quick Read or Write
Byte Read or Write
Byte Data Read or Write
Word Data Read or Write
Description
Bits[4:2]
100
101
110
111
Protocol
Reserved
Block Read or Write
Reserved
Reserved
Intel
®
82371EB (PIIX4E)
37