FW82371EB Intel, FW82371EB Datasheet - Page 12

• Manufacturer Part Number: FW82371EB
• Manufacturer: Intel

Specifications of FW82371EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
3.
12
®
82371EB (PIIX4E)
Enabling and Disabling Manual Throttling
For the PIIX4, the manual throttling state is initiated by setting CC_EN, THT_EN and reading the LVL2
register. A break event will disable throttling and another LVL2 read is required to restart throttling. On
the PIIX4E, break events will not disable manual throttling. Manual throttling mode begins when
CC_EN and THT_EN are set. Manual throttling mode is disabled when either CC_EN or THT_EN is
disabled.
This change applies to all steppings of the PIIX4E and will be incorporated into the next version of the
PIIX4 datasheet.
11.2.1 HOST CLOCK CONTROL MECHANISMS
Table 1. Clock Programming modes
System Throttle Control: If the system has been placed into the Stop Grant or Quick Start states and
[THT_EN] bit is set, PIIX4 toggles the STPCLK# signal and ZZ signal (If [ZZ_EN] set) with a period of
244 s (approximately 8 32 kHz clock periods) and a pprogramable duty cycle. This system toggles
between full-speed operation and the Stop Grant or Quick Start state. The duty cycle can be set in 12.5%
increments by programming the [THTL_DTY] bits in the Processor Control (P_CNTRL) register. This
emulates a reduced frequency Host clock, resulting in associated power savings.
Stop Break and Burst Execution: Once the hardware has been placed into a clock control state, it can
be restored to full operatin by system hardware or sofftware. Software can restore the system to full
operation by clearing the [CC_EN] bit. Hardware events can be enabled to return the system to a non-
clock controlled condition. If the [BRST_EN] bit is reset, these events are called Stop Break Events.
Alternatively, if the [BRST_EN] bit is set, thses events are called Burst Events.
Stop Break events completely return the system to non-clock controlled state. To restore clock control,
software must set the desired clock control configuration and again perform a read from LVL2 or LVL3
registers to initiate the control.
Note that Stop Break events do not halt Stop Grant/Quick Start with Throttle. The PIIX4E will continue
to throttle STPCLK#. Also note that if the system does a LVL2 read with CC_EN and THT_EN set, the
PIIX4E will enter the Stop Grant/Quick Start state without throttle. Upon a break event, the PIIX4E will
re-enter the Stop Grant/Quick Start state with Throttle.
Throttling begins upon
Clock Control Mode
Start without Throttle,
Start without Throttle
Start with Throttle
Stop Break Event
Stop Grant/Quick
Stop Grant/Quick
Stop Grant/Quick
Register Read
None Required
LVL 2
LVL 2
CC_E
N
1
1
1
STP_CLK_EN
X
X
X
SLEEP_EN
Specification Update
X
X
X
THT_EN
0
1
1
R