FW82371EB Intel, FW82371EB Datasheet - Page 14

• Manufacturer Part Number: FW82371EB
• Manufacturer: Intel

Specifications of FW82371EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
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82371EB (PIIX4E)
Thermal Break Enable
If THRM# is asserted for more than 2 seconds while the PIIX4 is in a Stop Grant state, the PIIX4 will
enter the thermal override state and begin throttling STPCLK# (see Specification Clarification #13).
Once THRM# is deasserted the PIIX4 will return to the previous clock control state. If break events are
disabled during the thermal override period the PiIIX4 will not be able to break out. Thermal break
enable offers a break event based on THRM# getting deasserted after Throttling from the thermal
override.
This change applies to all steppings of the PIIX4E and will be incorporated into the next revision of the
PIIX4 datasheet.
7.2.12
Aliased NMI Enable bit
The PIIX4 Datasheet, section 4.2.5.3 Real Time Clock Extended Index Register (IO), bit 7 description
changes from Reserved to Aliased NMI Enable. This bit must always reflect the state of the NMI Enable
bit, NMIEN[7] in IO space 70h.
IRQOUT# is Active Level HI
The PIIX4 Datacheet, and Datasheet Addendum, in several places identifies pin F3 (IRQ9OUT#/GP029)
as IRQ9OUT being active level LO. When IRQ9OUT functionality is selected, the IRQ9OUT is active
level HI, not active level LO. The name of this pin is changed to IRQ9OUT/Gpo29.
CLKRUN# Re-Assertion
The PIIX4 Datasheet on page 210, section 11.2.3, states if no other device in the system denies the
request to stop before the 5
request to stop before the 4
CNTB Granularity
The PIIX4 Datasheet, section 7.1.12, defines the Count B (Function 3) Register functionality. CNTB[5]
currently indicates that when this bit is set that the fast burst timer granularity is 1uS. This is incorrect,
the granularity, when CNTB[5] is set is 8uS.
This change applies to all steppings of the PIIX4 and will be incorporated into the next revision of the
PIIX4 datasheet.
Bit
2
GLBEN—GLOBAL ENABLE REGISTER (IO)
I/O Address:
Default Value: 00h
Attribute:
Thermal Break Enable (THRM_BK_EN) – R/W. 1=Generate a break event after THRM#
deassertion halts thermal throttling. 0=Disable
th
th
Base + (20h)
Read/Write
PCI clock, then the PIIX4 asserts the PCI_STP#. Any device must deny the
PCI clock.
Description
Specification Update
R