FW82371EB Intel, FW82371EB Datasheet - Page 34

• Manufacturer Part Number: FW82371EB
• Manufacturer: Intel

Specifications of FW82371EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
11.
12.
13.
14.
34
®
82371EB (PIIX4E)
SCI_EN Bit Clarification
The SCI_EN bit in the PMCNTRL register enables the generation of SCI from 4 sources; PWRBTN#,
LID, THRM#, and GPI1#. If this bit is enabled and the individual enable bits from these sources are set
(PWRBTN_EN, LID_EN, THRM_EN, and GPI_EN), an SCI is generated. If this bit is disabled and the
individual enable bits from these sources are set, an SMI# is generated. Note that there are two sources
of SCI (BIOS_RLS, TMROF_STS) that are not controlled by this register. To disable SCI from these
sources, their respective enable bits (GBL_EN, TMROF_EN) must be disabled.
This clarification applies to all steppings of the PIIX4 and will be incorporated into the next revision of
the PIIX4 datasheet.
7.2.3
I/O Address:
Default Value:
Attribute:
Thermal Override Initiates Throttling Even in Clock Control State
If THRM# is asserted for more than 2 seconds while the PIIX4 is in a Stop Grant state, the PIIX4 will
still initiate STPCLK# throttling. Once THRM# is deasserted the PIIX4 will return to the clock control
state.
This clarification applies to all steppings of the PIIX4 and PIIX4E and will be incorporated into the next
revision of the PIIX4 datasheet.
No Disabling Burst Events During A Burst
Burst events cause the reload of a Burst timer, which begins to count down from its loaded value. While
the timer is counting, the system returns to full clock operation. Once the burst timer expires, the system
automatically returns to the clock controlled state. PIIX4 provides 2 different burst timers, a fast burst
timer (which generates a short count) and a slow burst timer (which generates a longer count). If burst
events are disabled during a burst, the PIIX4 will enter the clock-controlled state after the burst timer
expires and will not be able to break out.
This clarification applies to all steppings of the PIIX4 and PIIX4E and will be incorporated into the next
revision of the PIIX4 datasheet.
Unrouting a PIRQ
Section 8.6.8, Interrupt Steering of the PIIX4 datasheet states how to route a PIRQx# to a IRQx, but does
not state a suggested procedure for unrouting. The paragraph below will be added at the end of this
section.
Before unrouting a PIRQx# from an IRQx, ensure that the mask is enabled for that IRQ and that the
corresponding ELCR is set back to edge mode. When the IRQx is unmasked an interrupt will likely be
generated which should be treated as any other spurious interrupt.
Bit
0
PMCNTRL POWER MANAGEMENT CONTROL REGISTER (IO)
LID_STS, THRM_STS, or GPI_STS bits. 0=Disable. Note that this register does not disable SCI
generation from the Power Management Timer or BIOS Release bit.
SCI Enable(SCI_EN)—R/W. 1=Enable generation of SCI upon setting of PWRBTN_STS,
Base + (04h)
0000h
Read/Write
Description
Specification Update
R