FW82371EB Intel, FW82371EB Datasheet - Page 36

• Manufacturer Part Number: FW82371EB
• Manufacturer: Intel

Specifications of FW82371EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
20.
36
®
82371EB (PIIX4E)
SMBus Busy Bit Behavior
In a polling environment, when reading the SMBus Host Status Register, the Host BUSY bit may appear
to indicate a premature transaction completion. Though the Host BUSY bit accurately tracks the SMBus
activity, there can be some delay between setting the start bit within the SMBus Controller and the
transaction actually starting. Immediate polling of the Host Status Register BUSY bit may indicate that
the SMBus is NOT busy, but the reason is because it hasn't started yet. Therefore, the suggested usage
model for non-BIOS implementations should be to use an interrupt or SMI to indicate when the
transaction is complete. The interrupt is guaranteed to follow the completion of the transaction because
the interrupt is an "AND" with the Interrupt Enable Bit and the Host Status Bit. This clarification applies
to all steppings of the PIIX4 and will be incorporated into the next revision of the PIIX4 datasheet.
To clarify this behavior, the following changes to the PIIX4 datasheet are required:
In the PIIX4 datasheet, Page 148, Section 7.3.1. SMBHSTSTS - SMBUS HOST STATUS REGISTER,
Bit 1 and Bit 0 should be changed to read:
7.3.1
I/O Address:
Default Value:
Attribute:
This register provides status information concerning the SMBus controller host interface.
In the PIIX4 datasheet, Page 150, Section 7.3.3. SMBHSTCNT - SMBUS HOST CONTROL
REGISTER (IO), Bit 0 should be changed to read:
7:5
Bit
4
3
2
1
0
SMBHSTSTS—SMBUS HOST STATUS REGISTER (IO)
Reserved.
Failed (FAILED)—R/WC. 1=Indicates that the source of SMBus interrupt was a failed bus
transaction, set when KILL bit is set (SMBHSTCNT register). 0=SMBus interrupt not caused by
KILL bit. This bit is only set by hardware and can only be reset by writing a 1 to this bit position.
BUS COLLISION (BUS_ERR)—R/WC. 1=Indicates that the source of SMBus interrupt was a
transaction collision. 0=SMBus interrupt not caused by transaction collision. This bit is only set by
hardware and can only be reset by writing a 1 to this bit position.
Device Error (DEV_ERR)—R/WC. 1=Indicates that the source of SMBus interrupt was the
generation of an SMBus transaction error. 0=SMBus interrupt not caused by transaction error.
This bit is only set by hardware and can only be reset by writing a 1 to this bit position. Transaction
errors are caused by:
SMBus Interrupt/Host Completion (INTER)—R/WC. 1= Indicates that the host transaction has
completed or that the source of an SMBus interrupt was the completion of the last host command.
0=Host transaction has not completed or that an SMBus interrupt was not caused by host
command completion. This bit is only set by hardware and can only be reset by writing a 1 to this
bit position.
Host Busy (HOST_BUSY)—RO. 1= Indicates that the SMBus controller host interface is in the
process of completing a command. 0=SMBus controller host interface is not processing a
command. None of the other registers should be accessed if this bit is set. Note that there may be
moderate latency before the transaction begins and the Host Busy bit gets set.
Base + (00h)
00h
Read/Write
Illegal Command Field
Unclaimed Cycle (host initiated)
Host Device Time-out
Description
Specification Update
R