FW82371EB Intel, FW82371EB Datasheet - Page 32

• Manufacturer Part Number: FW82371EB
• Manufacturer: Intel

Specifications of FW82371EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
8.
32
®
82371EB (PIIX4E)
SMI# Generation from APMC Write
In order to generate an SMI# by reading from the APMC Register it is necessary to enable both the
APMC_EN bit as well as the IOSE bit. The datasheet section 4.2.6.1, 7.1.3, and 7.1.16 does not state
that it is necessary to set the IOSE bit.
This clarification applies to all steppings of the PIIX4 and will be incorporated into the next revision of
the PIIX4 datasheet.
4.2.6.1
I/O Address:
Default Value:
Attribute:
This register passes data (APM Commands) between the OS and the SMI handler. In addition, writes can
generate an SMI. PIIX4 operation is not effected by the data in this register.
7.1.3
Address Offset:
Default Value:
Attribute:
This register controls access to the I/O space registers.
7.1.16
Address Offset:
Default Value:
Attribute:
This register contains the Clock Event and Global Timer Reload enables for IRQs, PCI access, PME
events, and Video.
7:0
Bit
Bit
Bit
25
0
APMC—Advanced Power Management Control Port (IO)
PCICMD—PCI COMMAND REGISTER (FUNCTION 3)
DEVACTB DEVICE ACTIVITY B (FUNCTION 3)
APM Control Port (APMC). Writes to this register store data in the APMC Register and reads
return the last data written. In addition, writes generate an SMI, if the APMC_EN bit (PCI function
3, offset 58h, bit 25) and the IOSE bit (PCI function 3, offset 04h, bit 0) are set to 1. Reads do not
generate an SMI.
I/O Space Enable (IOSE). 1=Enable. 0=Disable. This bit controls the access to the SMBus I/O
space registers whose base address is described in the SMBus Base Address register. If this bit is
set, access to the SMBus IO registers is enabled. The base register for the I/O registers must be
programmed before this bit is set. When disabled, all IO accesses associated with SMBus Base
Address are disabled. This bit must be set to enable SMI# generation from a write to the APMC
register. This bit functions independent of the state of Function 3 Power Management IO Space
Enable (PMIOSE) bit (PMREGMISC register, bit 0).
APMC Enable (APMC_EN)—R/W. 1=Enable generation of SMI# when APMC register is written to
and SMI# is enabled. 0=Disable.
0B2h
00h
Read/Write
04 05h
00h
Read/Write
58–5Bh
00h
Read/Write
Description
Description
Description
Specification Update
R