XC6SLX25-2FGG484C Xilinx Inc, XC6SLX25-2FGG484C Datasheet - Page 67

• Manufacturer Part Number: XC6SLX25-2FGG484C
• Description: FPGA Spartan®-6 Family 24051 Cells 45nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan® 6 LXr

Specifications of XC6SLX25-2FGG484C

• Package: 484FBGA
• Family Name: Spartan®-6
• Device Logic Cells: 24051
• Device Logic Units: 15000
• Number Of Registers: 30064
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 266
• Ram Bits: 958464
• Number Of Logic Elements/cells: 24051
• Number Of Labs/clbs: 1879
• Total Ram Bits: 958464
• Number Of I /o: 266
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-BBGA
• No. Of Logic Blocks: 3758
• No. Of Macrocells: 24051
• Family Type: Spartan-6
• No. Of Speed Grades: 2
• No. Of I/o's: 266
• Clock Management: DCM, PLL
• Core Supply Voltage Range: 1.14V
• Rohs Compliant: Yes
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 73: Global Clock Setup and Hold With DCM and PLL in System-Synchronous Mode
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Notes:
1.
2.
3.
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.
T
T
PSDCMPLL
PHDCMPLL
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock
input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using
the fastest process, lowest temperature, and highest voltage. These measurements include CMT jitter; DCM CLK0 driving PLL, PLL CLKOUT0
driving BUFG.
IFF = Input Flip-Flop or Latch
Use IBIS to determine any duty-cycle distortion incurred using various standards.
Symbol
/
No Delay Global Clock and IFF
System-Synchronous Mode and PLL in
DCM2PLL Mode.
Description
(2)
with DCM in
www.xilinx.com
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
XC6SLX4
XC6SLX9
XC6SLX16
XC6SLX25
XC6SLX25T
XC6SLX45
XC6SLX45T
XC6SLX75
XC6SLX75T
XC6SLX100
XC6SLX100T
XC6SLX150
XC6SLX150T
Device
–0.08
1.16/
1.16/
1.44/
1.52/
1.69/
1.54/
1.57/
1.72/
1.74/
1.34/
1.46/
1.30/
1.35/
0.49
0.44
0.42
0.42
0.39
0.39
0.41
0.41
0.51
0.51
0.60
0.60
-3
(1)
–0.04
1.37/
1.49/
1.65/
1.69/
1.59/
1.59/
1.80/
1.80/
1.46/
1.46/
1.40/
1.40/
0.44
0.42
0.42
0.39
0.39
0.41
0.41
0.51
0.51
0.60
0.60
Speed Grade
-3N
N/A
–0.04
1.39/
1.39/
1.75/
1.75/
1.99/
1.99/
1.64/
1.64/
1.55/
1.55/
0.49
0.44
1.62
1.83
0.42
1.83
0.42
0.39
0.39
0.41
0.41
0.51
0.51
0.60
0.60
-2
2.36/
2.36/
2.06/
2.52/
2.48/
2.60/
2.12/
2.57/
0.59
0.59
0.55
0.43
0.76
0.75
0.90
0.97
N/A
N/A
N/A
N/A
N/A
-1L
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
67