XC6SLX25-2FGG484C Xilinx Inc, XC6SLX25-2FGG484C Datasheet - Page 59

• Manufacturer Part Number: XC6SLX25-2FGG484C
• Description: FPGA Spartan®-6 Family 24051 Cells 45nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan® 6 LXr

Specifications of XC6SLX25-2FGG484C

• Package: 484FBGA
• Family Name: Spartan®-6
• Device Logic Cells: 24051
• Device Logic Units: 15000
• Number Of Registers: 30064
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 266
• Ram Bits: 958464
• Number Of Logic Elements/cells: 24051
• Number Of Labs/clbs: 1879
• Total Ram Bits: 958464
• Number Of I /o: 266
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-BBGA
• No. Of Logic Blocks: 3758
• No. Of Macrocells: 24051
• Family Type: Spartan-6
• No. Of Speed Grades: 2
• No. Of I/o's: 266
• Clock Management: DCM, PLL
• Core Supply Voltage Range: 1.14V
• Rohs Compliant: Yes
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 63: Global Clock Input to Output Delay With DCM in Source-Synchronous Mode
Table 64: Global Clock Input to Output Delay With PLL in System-Synchronous Mode
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Notes:
1.
2.
Notes:
1.
2.
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in Source-Synchronous Mode.
T
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL in System-Synchronous Mode.
T
ICKOFDCM_0
ICKOFPLL
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible
IOB and CLB flip-flops are clocked by the global clock net.
DCM output jitter is already included in the timing calculation.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible
IOB and CLB flip-flops are clocked by the global clock net.
PLL output jitter is included in the timing calculation.
Symbol
Symbol
Global Clock and OUTFF with DCM
Global Clock and OUTFF with PLL
Description
Description
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
XC6SLX4
XC6SLX9
XC6SLX16
XC6SLX25
XC6SLX25T
XC6SLX45
XC6SLX45T
XC6SLX75
XC6SLX75T
XC6SLX100
XC6SLX100T
XC6SLX150
XC6SLX150T
XC6SLX4
XC6SLX9
XC6SLX16
XC6SLX25
XC6SLX25T
XC6SLX45
XC6SLX45T
XC6SLX75
XC6SLX75T
XC6SLX100
XC6SLX100T
XC6SLX150
XC6SLX150T
Device
Device
5.03
5.08
4.81
5.26
4.77
4.72
4.76
4.90
4.90
4.57
4.41
4.03
4.63
4.01
4.02
4.06
3.65
3.65
5.03
4.81
5.26
4.77
4.57
4.03
4.63
4.01
-3
-3
6.13
5.51
5.13
5.13
5.69
5.69
5.18
5.18
5.11
5.11
5.30
5.30
5.25
4.64
4.32
4.32
4.96
4.96
4.30
4.30
4.33
4.33
3.98
3.98
Speed Grade
Speed Grade
-3N
N/A
-3N
N/A
7.21
7.21
6.44
5.69
5.69
6.63
6.63
5.88
5.88
5.76
5.76
5.93
5.93
6.25
6.25
5.39
4.91
4.91
5.75
5.75
4.88
4.88
4.90
4.90
4.58
4.58
-2
-2
8.05
8.05
7.96
7.94
7.92
7.95
8.59
7.93
7.34
7.34
6.92
7.64
7.36
7.15
7.37
6.94
N/A
N/A
N/A
N/A
-1L
N/A
N/A
N/A
-1L
N/A
N/A
N/A
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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