XC6SLX25-2FGG484C Xilinx Inc, XC6SLX25-2FGG484C Datasheet - Page 42

• Manufacturer Part Number: XC6SLX25-2FGG484C
• Description: FPGA Spartan®-6 Family 24051 Cells 45nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan® 6 LXr

Specifications of XC6SLX25-2FGG484C

• Package: 484FBGA
• Family Name: Spartan®-6
• Device Logic Cells: 24051
• Device Logic Units: 15000
• Number Of Registers: 30064
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 266
• Ram Bits: 958464
• Number Of Logic Elements/cells: 24051
• Number Of Labs/clbs: 1879
• Total Ram Bits: 958464
• Number Of I /o: 266
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-BBGA
• No. Of Logic Blocks: 3758
• No. Of Macrocells: 24051
• Family Type: Spartan-6
• No. Of Speed Grades: 2
• No. Of I/o's: 266
• Clock Management: DCM, PLL
• Core Supply Voltage Range: 1.14V
• Rohs Compliant: Yes
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Block RAM Switching Characteristics
Table 42: Block RAM Switching Characteristics
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Notes:
1.
2.
3.
4.
Block RAM Clock to Out Delays
T
Setup and Hold Times Before/After Clock CLK
T
T
T
T
T
Maximum Frequency
F
T
RCKO_DO
RCCK_ADDR
RDCK_DI
RCCK_EN
RCCK_REGCE
RCCK_WE
MAX
RCKO_DO_REG
T
T
The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible.
T
RCKO_DO
RCKO_DO_REG
RDCK_DI
/T
/T
/T
RCKD_DI
RCKC_EN
Symbol
RCKC_WE
/T
includes both A and B inputs as well as the parity inputs of A and B.
includes T
/T
RCKC_ADDR
RCKC_REGCE
includes T
RCKO_DOA
RCKO_DOA_REG
and T
Clock CLK to DOUT output (without output register)
Clock CLK to DOUT output (with output register)
ADDR inputs
DIN inputs
Block RAM Enable (EN) input
CE input of output register
Write Enable (WE) input
Block RAM in all modes
RCKO_DOPA
and T
(4)
RCKO_DOPA_REG
(3)
as well as the B port equivalent timing parameters.
Description
www.xilinx.com
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
as well as the B port equivalent timing parameters.
(2)
(1)
1.85
1.60
0.35
0.10
0.30
0.10
0.22
0.05
0.20
0.10
0.25
0.10
320
-3
Speed Grade
2.10
1.75
0.40
0.12
0.30
0.10
0.22
0.06
0.20
0.10
0.33
0.10
-3N
280
2.10
1.75
0.40
0.12
0.30
0.10
0.22
0.06
0.20
0.10
0.33
0.10
260
-2
3.50
2.30
0.50
0.15
0.40
0.15
0.44
0.10
0.28
0.15
0.28
0.15
150
-1L
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
Units
MHz
42