ISP1508AET NXP Semiconductors, ISP1508AET Datasheet - Page 57

• Manufacturer Part Number: ISP1508AET
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1508AET

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935283548118 ISP1508AET-T

NXP Semiconductors
Table 42.
Table 43.
Table 44.
Table 45.
ISP1508A_ISP1508B_1
Product data sheet
Bit
7 to 5
4
3
2
1
0
Bit
Symbol
Reset
Access
Bit
7 to 2
1
0
Bit
7 to 0
Symbol
SCRATCH[7:0]
Symbol
-
ID_GND_L
SESS_END_L
SESS_VALID_L
VBUS_VALID_L
HOST_DISCON_L
USB Interrupt Latch register (address R = 14h) bit description
Debug register (address R = 15h) bit allocation
Debug register (address R = 15h) bit description
Scratch register (address R = 16h to 18h, W = 16h, S = 17h, C = 18h) bit description
11.10 Scratch register
11.11 Carkit Control register
11.9 Debug register
Symbol
-
LINESTATE1
LINESTATE0
R
7
0
The bit allocation of the Debug register is given in
current value of signals useful for debugging.
This is a 1-byte empty register for testing purposes, see
This register controls transparent UART mode. This register is only valid when the
CARKIT_MODE register bit in the Interface Control register is set. When entering UART
mode, set the CARKIT_MODE bit, and then set the TXD_EN and RXD_EN bits. After
entering UART mode, the ULPI interface is not available. When exiting UART mode,
assert the STP pin or perform a hardware reset using the CHIP_SEL pin.
Access
R/W/S/C
Description
reserved
ID Ground Latch: Automatically set when an unmasked event occurs on ID_GND. Cleared
when this register is read.
Session End Latch: Automatically set when an unmasked event occurs on SESS_END.
Cleared when this register is read.
Session Valid Latch: Automatically set when an unmasked event occurs on SESS_VLD.
Cleared when this register is read.
V
Cleared when this register is read.
Host Disconnect Latch: Automatically set when an unmasked event occurs on
HOST_DISCON. Cleared when this register is read.
R
6
0
BUS
Description
reserved
Line State 1: Contains the current value of LINESTATE 1.
Line State 0: Contains the current value of LINESTATE 0.
Valid Latch: Automatically set when an unmasked event occurs on A_VBUS_VLD.
Value
00h
R
5
0
Rev. 01 — 14 August 2007
reserved
Description
Scratch: This is an empty register byte for testing purposes. Software
can read, write, set and clear this register, and the functionality of the
PHY will not be affected.
R
4
0
R
3
0
ISP1508A; ISP1508B
Table
43. This register indicates the
Table
R
2
0
45.
ULPI HS USB transceiver
STATE1
LINE
R
1
0
© NXP B.V. 2007. All rights reserved.
STATE0
LINE
R
0
0
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