ISP1508AET NXP Semiconductors, ISP1508AET Datasheet - Page 25

• Manufacturer Part Number: ISP1508AET
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1508AET

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935283548118 ISP1508AET-T

NXP Semiconductors
ISP1508A_ISP1508B_1
Product data sheet
After the register configuration is complete:
By default, the clock is powered down when the ISP1508 enters UART mode. If the link
requires CLOCK to be running in UART mode, it can set the CLOCK_SUSPENDM bit in
the Interface Control register to logic 1 before entering UART mode.
Transparent UART mode is exited by asserting the STP pin to HIGH or by toggling the
CHIP_SEL pin.
The INT pin is asserted and latched whenever an unmasked interrupt event occurs. When
the link detects INT as HIGH, it must wake-up the PHY from transparent UART mode by
asserting STP. When the PHY is in synchronous mode, the link can read the USB
Interrupt Latch register to determine the source of the interrupt. Note that the ISP1508
does not implement the optional Carkit Interrupt registers.
An alternative way to exit UART mode is to set the CHIP_SEL pin to non-active for more
than t
will be put in default synchronous mode.
1. A weak pull-up resistor will be enabled on the DP and DATA0 pins. This is to avoid the
2. The 39
3. One clock cycle after DIR goes from LOW to HIGH, the ISP1508 will drive the data
4. UART buffers between DATA0 or DATA1 and DM or DP are enabled. Transparent
possible floating condition on these input pins when UART mode is enabled.
bus for five clock cycles. This is to charge the DATA0 pin to a HIGH level for a slow
link. The link, however, can start driving DATA0 to HIGH immediately after the
turnaround cycle.
UART mode is entered.
Remark: The DP pin will be slowly charged up to HIGH by the weak pull-up resistor.
The time needed depends on the capacitive loading on DP.
PWRDN
and then set it to active. A power-on reset will be generated and the ULPI bus
serial termination resistors on the DP and DM pins will be enabled.
Rev. 01 — 14 August 2007
ISP1508A; ISP1508B
ULPI HS USB transceiver
© NXP B.V. 2007. All rights reserved.
25 of 86