ISP1508AET NXP Semiconductors, ISP1508AET Datasheet - Page 17

• Manufacturer Part Number: ISP1508AET
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1508AET

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935283548118 ISP1508AET-T

NXP Semiconductors
ISP1508A_ISP1508B_1
Product data sheet
8.11 Power-up, reset and bus idle sequence
Figure 6
On power-up, the ISP1508 performs an internal power-on reset and asserts DIR to
indicate to the link that the ULPI bus cannot be used. When the internal PLL is stable, the
ISP1508 de-asserts DIR and drives 60 MHz clock out from the CLOCK pin. The power-up
time depends on the V
t
default, the link must drive data to LOW. Before beginning USB packets, the link must set
the RESET bit in the Function Control register to reset the ISP1508. After the RESET bit
is set, the ISP1508 will assert DIR until the internal reset completes. The ISP1508 will
automatically de-assert DIR and clear the RESET bit when the reset has completed. After
every reset, an RXCMD is sent to the link to update USB status information. After this
sequence, the ULPI bus is ready for use and the link can start USB operations.
If V
power-down mode. In power-down mode, all ULPI interface pins will be put in 3-state, the
internal regulator will be shut down, and the total power current from V
I
The link can do a hardware reset to the ISP1508 by toggling the CHIP_SEL pin. The
recommended sequence is:
The recommended power-up sequence for the link is:
The ULPI interface is ready for use.
startup(PLL)
CC
1. De-activate the CHIP_SEL pin.
2. Wait for at least t
3. Activate the CHIP_SEL pin.
1. Apply the V
2. Activate the CHIP_SEL pin.
3. The link waits for at least t
4. The link may start to detect the DIR status level. If DIR is detected LOW, the link may
Fig 5. Internal power-on reset timing
CC(I/O)
in power-down mode.
send a RESET command.
shows a typical start-up sequence.
is not present or the CHIP_SEL pin is non-active, the ISP1508 will be kept in
. When DIR is de-asserted, the link must drive the data bus to a valid level. By
t0
CC
t1
and V
PWRDN
Rev. 01 — 14 August 2007
CC
CC(I/O)
supply rise time, the crystal start-up time, and PLL start-up time
.
PWRUP
power.
, ignoring all the ULPI pin status.
t2
ISP1508A; ISP1508B
t3
t4
t5
ULPI HS USB transceiver
CC
© NXP B.V. 2007. All rights reserved.
004aab023
REG1V8
V
POR
will be less than
POR(trip)
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