ISP1508AET NXP Semiconductors, ISP1508AET Datasheet - Page 18

• Manufacturer Part Number: ISP1508AET
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1508AET

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935283548118 ISP1508AET-T

NXP Semiconductors
ISP1508A_ISP1508B_1
Product data sheet
Fig 6. Power-up and reset sequence required before the ULPI bus is ready for use
CHIP_SEL
DATA[7:0]
REG1V8
V
Internal
CLOCK
(output)
CC(I/O)
XTAL1
POR
t1 = V
t2 = V
non-active.
t3 = CHIP_SEL turns from non-active to active. The ISP1508 regulator starts to turn on. ULPI pads are not in 3-state and
may either drive to LOW or HIGH. It is recommended that the link ignores ULPI pins status during t
t4 = Power-on reset threshold is reached and the POR pulse is generated. After the POR pulse, ULPI pins are driven to a
defined level. DIR is driven to HIGH and the other pins are driven to LOW.
t5 = The PLL is stabilized after t
from HIGH to LOW. The link must drive DATA[7:0] and STP to LOW as idle state. The link will then issue a reset command
to initialize the ISP1508.
t6 = The power-up sequence is completed and the ULPI bus interface is ready for use.
V
NXT
STP
DIR
CC
t1
CC
CC(I/O)
8.11.1 Interface protection
is applied to the ISP1508.
t2
is turned on. ULPI interface pins CLOCK, DATA[7:0], DIR and NXT are in 3-state as long as CHIP_SEL is
t3
By default, the ISP1508 enables a weak pull-up resistor on STP. If the STP pin is
unexpectedly HIGH at any time, the ISP1508 will protect the ULPI interface by enabling
weak pull-down resistors on DATA[7:0].
t
PWRUP
t4
d(det)clk(osc)
t
d(det)clk(osc)
+ t
startup(PLL)
Rev. 01 — 14 August 2007
+ t
startup(PLL)
. The CLOCK pin starts to output 60 MHz. The DIR pin will transition
t5
internal clocks stable
RESET command
TXCMD
D
ISP1508A; ISP1508B
internal reset
ULPI HS USB transceiver
PWRUP
.
© NXP B.V. 2007. All rights reserved.
RXCMD
update
004aaa870
bus idle
t6
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