CY8C3866AXI-040 Cypress Semiconductor Corp, CY8C3866AXI-040 Datasheet - Page 49

PSOC 3 TQFP

CY8C3866AXI-040

Manufacturer Part Number
CY8C3866AXI-040
Description
PSOC 3 TQFP
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ 3 CY8C38xxr
Datasheet

Specifications of CY8C3866AXI-040

Package / Case
*
Voltage - Supply (vcc/vdd)
1.71 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
67MHz
Number Of I /o
62
Eeprom Size
2K x 8
Core Processor
8051
Program Memory Type
FLASH
Ram Size
8K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 2x20b, D/A 4x8b
Oscillator Type
Internal
Peripherals
CapSense, DMA, LCD, POR, PWM, WDT
Connectivity
CAN, EBI/EMI, I²C, LIN, SPI, UART/USART, USB
Core Size
8-Bit
Processor Series
CY8C38
Core
8051
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART, USB
Maximum Clock Frequency
67 MHz
Number Of Programmable I/os
28 to 72
Number Of Timers
4
Operating Supply Voltage
0.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Controller Family/series
(8051) PSOC 3
No. Of I/o's
62
Eeprom Memory Size
2KB
Ram Memory Size
8KB
Cpu Speed
67MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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7.6 USB
PSoC includes a dedicated Full-Speed (12 Mbps) USB 2.0
transceiver supporting all four USB transfer types: control,
interrupt, bulk, and isochronous. PSoC Creator provides full
configuration support. USB interfaces to hosts through two
dedicated USBIO pins, which are detailed in the
Routing”
USB includes the following features:
Document Number: 001-11729 Rev. *R
RxInterrupt
(if enabled)
Eight unidirectional data endpoints
One bidirectional control endpoint 0 (EP0)
Shared 512-byte buffer for the eight data endpoints
Dedicated 8-byte buffer for EP0
Three memory modes
Internal 3.3-V regulator for transceiver
Request
Manual memory management with no DMA access
Manual memory management with manual DMA access
Automatic memory management with automatic DMA
access
section on page 33.
RxMessage
Rx Buffer
Available
Status
(if enabled)
TxInterrupt
RxMessage14
RxMessage15
RxMessage0
RxMessage1
Request
Tx Buffer
Pending
TxReq
Status
Acceptance Code 14
Acceptance Code 15
Acceptance Code 0
Acceptance Code 1
Figure 7-19. CAN Controller Block Diagram
“I/O System and
RTR RxMessages
TxMessage0
TxReq
TxAbort
TxMessage1
TxReq
TxAbort
TxMessage6
TxReq
TxAbort
TxMessage7
TxReq
TxAbort
0-15
Acceptance Mask 14
Acceptance Mask 15
Acceptance Mask 0
Acceptance Mask 1
Figure 7-20. USB
Internal 48-MHz main oscillator mode that auto locks to USB
bus clock, requiring no external crystal for USB (USB equipped
parts only)
Interrupts on bus and each endpoint event, with device wakeup
USB reset, suspend, and resume operations
Bus-powered and self-powered modes
Interrupts
(Serial Interface
Engine)
48 MHz
Arbiter
RxMessage
ErrInterrupt
(if enabled)
S I E
IMO
Request
Handler
Priority
Arbiter
PSoC
Error Status
512 X 8
Error Detection
SRAM
Framer
Framer
Tx Error Counter
Rx Error Counter
CAN
CAN
Rx
Tx
USB
CRC
Form
ACK
Bit Stuffing
Bit Error
Overload
Arbitration
®
I/O
Error Active
Error Passive
Bus Off
3: CY8C38 Family
CRC Check
Generator
CRC
D+
D–
External 22 Ω
Data Sheet
Resistors
Bit Timing
Page 49 of 129
WakeUp
Request
Tx
Rx
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