CY8C3866AXI-040 Cypress Semiconductor Corp, CY8C3866AXI-040 Datasheet - Page 43

• Manufacturer Part Number: CY8C3866AXI-040
• Description: PSOC 3 TQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C38xxr

Specifications of CY8C3866AXI-040

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 67MHz
• Number Of I /o: 62
• Eeprom Size: 2K x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 2x20b, D/A 4x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, LCD, POR, PWM, WDT
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, UART/USART, USB
• Core Size: 8-Bit
• Processor Series: CY8C38
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 67 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 0.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 62
• Eeprom Memory Size: 2KB
• Ram Memory Size: 8KB
• Cpu Speed: 67MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The main component blocks of the UDB are:
7.2.1 PLD Module
The primary purpose of the PLD blocks is to implement logic
expressions, state machines, sequencers, lookup tables, and
decoders. In the simplest use model, consider the PLD blocks as
a standalone resource onto which general purpose RTL is
synthesized and mapped. The more common and efficient use
model is to create digital functions from a combination of PLD
and datapath blocks, where the PLD implements only the
random logic and state portion of the function while the datapath
(ALU) implements the more structured elements.
Document Number: 001-11729 Rev. *R
PLD blocks – There are two small PLDs per UDB. These blocks
take inputs from the routing array and form registered or
combinational sum-of-products logic. PLDs are used to
implement state machines, state bits, and combinational logic
equations. PLD configuration is automatically generated from
graphical primitives.
Datapath module – This 8-bit wide datapath contains structured
logic to implement a dynamically configurable ALU, a variety
of compare configurations and condition generation. This block
also contains input/output FIFOs, which are the primary parallel
data interface between the CPU/DMA system and the UDB.
Status and control module – The primary role of this block is to
provide a way for CPU firmware to interact and synchronize
with UDB operation.
Clock and reset module – This block provides the UDB clocks
and reset selection and control.
Figure 7-7. PLD 12C4 Structure
OUT0
OUT1
OUT2
One 12C4 PLD block is shown in
inputs, which feed across eight product terms. Each product term
(AND function) can be from 1 to 12 inputs wide, and in a given
product term, the true (T) or complement (C) of each input can
be selected. The product terms are summed (OR function) to
create the PLD outputs. A sum can be from 1 to 8 product terms
wide. The 'C' in 12C4 indicates that the width of the OR gate (in
this case 8) is constant across all outputs (rather than variable
as in a 22V10 device). This PLA like structure gives maximum
flexibility and insures that all inputs and outputs are permutable
for ease of allocation by the software tools. There are two 12C4
PLDs in each UDB.
OUT3
(carry out)
(carry in)
SELOUT
SELIN
MC0
MC1
MC2
MC3
IN10
IN11
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
PSoC
T C
T C
T C
T C
T C
T C
T C
T C
T C
T C
T C
T C
T
T
T
T
T C
T C
T C
T C
T C
T C
T C
T C
T C
T C
T C
T C
T
T
T
T
T C
T C
T C
T C
T C
T C
T C
T C
T C
T C
T C
T C
®
T
T
T
T
3: CY8C38 Family
T C
T C
T C
T C
T C
T C
T C
T C
T C
T C
T C
T C
Figure
T
T
T
T
Array
OR
T C
T C
T C
T C
T C
T C
T C
T C
T C
T C
T C
T C
T
T
T
T
7-7. This PLD has 12
T C
T C
T C
T C
T C
T C
T C
T C
T C
T C
T C
T C
T
T
T
T
Data Sheet
T C
T C
T C
T C
T C
T C
T C
T C
T C
T C
T C
T C
T
T
T
T
Page 43 of 129
T C
T C
T C
T C
T C
T C
T C
T C
T C
T C
T C
T C
T
T
T
T
Array
AND
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