P89CV51RC2FA NXP Semiconductors, P89CV51RC2FA Datasheet - Page 58

• Manufacturer Part Number: P89CV51RC2FA
• Description: MCU 8-Bit 89C 80C51 CISC 32KB Flash 5V 44-Pin PLCC Tube
• Manufacturer: NXP Semiconductors

Specifications of P89CV51RC2FA

• Package: 44PLCC
• Device Core: 80C51
• Family Name: 89C
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: SPI/UART
• Number Of Timers: 3
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C

NXP Semiconductors
P89CV51RB2_RC2_RD2_3
Product data sheet
6.13.1.1 Clock control register (CKCON)
By default, the device runs at twelve clock cycles per machine cycle (12-clock mode). The
device may be run at 6 clock cycles per machine cycle (6-clock mode) by programming of
either a non-volatile bit (FX2) or an SFR bit (X2); see
non-volatile bit is programmed, the device will run in 6-clock mode and the X2 SFR bit has
no effect. If the FX2 bit is erased, then the clock mode is controlled by the X2 SFR bit.
Table 50.
Not bit addressable; reset value 00H.
Table 51.
Table 52.
Bit
Symbol
Bit
7
6
5
4
3
2
1
0
FX2 clock mode bit X2 bit
erased
programmed
CKCON - Clock control register (address 8FH) bit allocation
CKCON - Clock control register (address 8FH) bit description
Clock modes
SPIX2
Symbol
SPIX2
WDX2
PCAX2
SIX2
T2X2
T1X2
T0X2
X2
7
0
1
X
WDX2
Rev. 03 — 25 August 2009
6
Description
SPI clock; 0 = 6 clock cycles for each SPI clock cycle;
1 = 12 clock cycles
Watchdog clock; 0 = 6 clock cycles for each WDT clock cycle;
1 = 12 clock cycles
PCA clock; 0 = 6 clock cycles for each PCA clock cycle;
1 = 12 clock cycles
UART clock; 0 = 6 clock cycles for each UART clock cycle;
1 = 12 clock cycles
Timer 2 clock; 0 = 6 clock cycles for each Timer 2 clock cycle;
1 = 12 clock cycles
Timer 1 clock; 0 = 6 clock cycles for each Timer 1 clock cycle;
1 = 12 clock cycles
Timer 0 clock; 0 = 6 clock cycles for each Timer 0 clock cycle;
1 = 12 clock cycles
CPU clock; 0 = 12 clock cycles for each machine cycle;
1 = 6 clock cycles
CPU clock mode
12-clock (default)
6-clock
6-clock
PCAX2
5
P89CV51RB2/RC2/RD2
SIX2
4
Peripheral clock
mode bit (e.g. T0X2)
X
0
1
0
1
T2X2
Table 52 “Clock
3
80C51 with 1 kB RAM, SPI
T1X2
2
modes”. If the FX2
© NXP B.V. 2009. All rights reserved.
Mode
12-clock (default)
6-clock
12-clock
6-clock
12-clock
T0X2
1
58 of 76
X2
0