P89CV51RC2FA NXP Semiconductors, P89CV51RC2FA Datasheet - Page 43

• Manufacturer Part Number: P89CV51RC2FA
• Description: MCU 8-Bit 89C 80C51 CISC 32KB Flash 5V 44-Pin PLCC Tube
• Manufacturer: NXP Semiconductors

Specifications of P89CV51RC2FA

• Package: 44PLCC
• Device Core: 80C51
• Family Name: 89C
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: SPI/UART
• Number Of Timers: 3
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C

NXP Semiconductors
P89CV51RB2_RC2_RD2_3
Product data sheet
6.8 Watchdog timer
Table 30.
Reset source(s): any reset; reset value: 0000 0000B.
Table 31.
The WDT is intended as a recovery method in situations where the CPU may be
subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog
Timer Reset (WDTRST) SFR. The WDT is disabled at reset. To enable the WDT, the user
must write 01EH and 0E1H, in sequence, to the WDTRST SFR. When the WDT is
enabled, it will increment every machine cycle while the oscillator is running. There is no
Bit
Symbol
Bit
7
6
5 to 0
Fig 17. SPI transfer format with CPHA = 0
Fig 18. SPI transfer format with CPHA = 1
SCK (CPOL = 0)
SCK (CPOL = 1)
SCK (CPOL = 0)
SCK (CPOL = 1)
(for reference)
(for reference)
(from master)
(from master)
SS (to slave)
SS (to slave)
SCK cycle #
SCK cycle #
(from slave)
(from slave)
SPSR - SPI Status Register (address AAH) bit allocation
SPSR - SPI Status Register (address AAH) bit description
SPIF
Symbol
SPIF
WCOL
-
MOSI
MISO
MOSI
MISO
7
WCOL
Rev. 03 — 25 August 2009
6
Description
SPI interrupt flag. Upon completion of data transfer, this bit is set to 1.
If SPIE = 1 and ES = 1, an interrupt is then generated. This bit is
cleared by software.
Write Collision flag. Set if the SPI data register is written to during data
transfer. This bit is cleared by software.
Reserved for future use. Should be set to 0 by user programs.
MSB
MSB
MSB
MSB
1
1
2
2
6
6
5
6
6
-
3
3
5
5
P89CV51RB2/RC2/RD2
5
5
4
-
4
4
4
4
4
4
5
5
3
3
3
3
3
-
6
6
2
2
2
2
80C51 with 1 kB RAM, SPI
7
7
1
1
1
1
2
-
LSB
8
LSB
LSB
8
© NXP B.V. 2009. All rights reserved.
LSB
1
-
002aaa529
002aaa530
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0
-