N25Q128A13BSF40G NUMONYX, N25Q128A13BSF40G Datasheet - Page 40

• Manufacturer Part Number: N25Q128A13BSF40G
• Description: SERIAL NOR
• Manufacturer: NUMONYX

Table 5.
6.3.1
Note:
40/180
VCR<7:4>
VCR<3>
VCR<2:0>
Bit
Volatile Configuration Register
Dummy clock cycle: VCR bits 7 to 4
The bits from 7 to 4 of the Volatile Configuration Register, as the bits from 15 to 12 of the
Volatile Configuration register, set the dummy clock cycles number after the fast read
instructions (in all the 3 available protocols). The dummy clock cycles number can be set
from 1 up to 15 as described in
operating frequency (the higher is the operating frequency, the bigger must be the dummy
clock cycle number, according to
the fast read instructions performance.
If the dummy clock number is not sufficient for the operating frequency, the memory reads
wrong data.
Dummy clock
cycle
XIP
Reserved
Parameter
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
xxx
Value
As '1111'
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Target on maximum
allowed frequency fc
(108MHz) and to
guarantee backward
compatibility (default)
Ready to enter XIP mode To make the data on DQ0 during the first
XIP disabled (default)
reserved
Table 5.: Volatile Configuration
Table 4.: Maximum allowed frequency
Description
To optimize instruction execution
(FASTREAD, DOFR,DIOFR,QOFR,
QIOFR, ROTP) according to the frequency
dummy clock NOT “Don’t Care.” For
devices with feature set digit equal to 2 or 4
in the part number (Basic XiP), this bit is
always Don't Care"
Fixed value = 000b
Register, according to
Note
(MHz)) to optimize