N25Q128A13BSF40G NUMONYX, N25Q128A13BSF40G Datasheet - Page 157

• Manufacturer Part Number: N25Q128A13BSF40G
• Description: SERIAL NOR
• Manufacturer: NUMONYX

10.1
Yes
XiP Confirmation
Is XIP enabled ?
NVCR Check
Figure 96. N25Q128 Read functionality Flow Chart
Enter XIP mode by setting the Non Volatile Configuration
Register
To use the Non Volatile Configuration Register method to enter in XIP mode it is necessary
to set the Non Volatile Configuration Register bits from 11 to 9 with the pattern
corresponding to the required XIP mode by mean of the Write Non Volatile Configuration
Register (WRNVCR) instruction. (See
This instruction doesn't affect the XIP state until the next Power on sequence. In this case,
after the next power on sequence, the memory directly accept addresses and then, after the
dummy clock cycles (configurable), outputs the data as described in
bits setting
protocol with six dummy clock cycles the following pattern must be issued:
Power On
XIP mode
bit = 0 ?
Yes
example. For example to enable fast POR and XIP on QIOFR in normal SPI
No
No
SPI standard mode (no
XiP, VCR <3> = 1)
Table 24.: NVCR XIP bits setting
VCR<3> = 0 ?
No
Yes
No
SPI mode (no XIP) but
Read Instructions ?
ready to enter XIP
XiP Confirmation
Table 24.: NVCR XIP
bit = 0 ?
example.)
Yes
Yes
No
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