MT48LC16M16A2P-75 IT:D TR Micron Technology Inc, MT48LC16M16A2P-75 IT:D TR Datasheet - Page 78
![DRAM Chip SDRAM 256M-Bit 16Mx16 3.3V 54-Pin TSOP-II T/R](/photos/7/22/72261/557-54-tsop_sml.jpg)
MT48LC16M16A2P-75 IT:D TR
Manufacturer Part Number
MT48LC16M16A2P-75 IT:D TR
Description
DRAM Chip SDRAM 256M-Bit 16Mx16 3.3V 54-Pin TSOP-II T/R
Manufacturer
Micron Technology Inc
Type
SDRAMr
Specifications of MT48LC16M16A2P-75 IT:D TR
Density
256 Mb
Maximum Clock Rate
133 MHz
Package
54TSOP-II
Address Bus Width
15 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
6|5.4 ns
Operating Temperature
-40 to 85 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
256M (16Mx16)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
54-TSOP II
Organization
16Mx16
Address Bus
15b
Access Time (max)
6/5.4ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
135mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
557-1058-2
Command
Figure 48: WRITE Without Auto Precharge
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
BA0, BA1
Address
DQM
CKE
A10
CLK
DQ
t CMS
t CKS
t AS
t AS
t AS
Bank
ACTIVE
Row
Row
T0
t CKH
t CMH
t AH
t AH
t AH
t RCD
t RAS
t RC
t CK
Note:
T1
NOP
Disable auto precharge
1. For this example, BL = 4 and the WRITE burst is followed by a manual PRECHARGE.
t CMS
t CL
Column m
t DS
WRITE
Bank
T2
D
IN
t CMH
t DH
t CH
t DS
T3
NOP
D
IN
t DH
t DS
T4
NOP
D
IN
t DH
78
t DS
NOP
T5
D
IN
t DH
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t WR
NOP
T6
256Mb: x4, x8, x16 SDRAM
PRECHARGE
Single bank
All banks
PRECHARGE Operation
Bank
T7
© 1999 Micron Technology, Inc. All rights reserved.
t RP
NOP
T8
ACTIVE
Row
Row
Bank
T9
Don’t Care