MT48LC16M16A2P-75 IT:D TR Micron Technology Inc, MT48LC16M16A2P-75 IT:D TR Datasheet - Page 43
![DRAM Chip SDRAM 256M-Bit 16Mx16 3.3V 54-Pin TSOP-II T/R](/photos/7/22/72261/557-54-tsop_sml.jpg)
MT48LC16M16A2P-75 IT:D TR
Manufacturer Part Number
MT48LC16M16A2P-75 IT:D TR
Description
DRAM Chip SDRAM 256M-Bit 16Mx16 3.3V 54-Pin TSOP-II T/R
Manufacturer
Micron Technology Inc
Type
SDRAMr
Specifications of MT48LC16M16A2P-75 IT:D TR
Density
256 Mb
Maximum Clock Rate
133 MHz
Package
54TSOP-II
Address Bus Width
15 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
6|5.4 ns
Operating Temperature
-40 to 85 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
256M (16Mx16)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
54-TSOP II
Organization
16Mx16
Address Bus
15b
Access Time (max)
6/5.4ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
135mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
557-1058-2
Initialization
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
SDRAM must be powered up and initialized in a predefined manner. Operational proce-
dures other than those specified may result in undefined operation. After power is
applied to V
as a signal cycling within timing constraints specified for the clock pin), the SDRAM re-
quires a 100μs delay prior to issuing any command other than a COMMAND INHIBIT
or NOP. Starting at some point during this 100μs period and continuing at least through
the end of this period, COMMAND INHIBIT or NOP commands must be applied.
After the 100μs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All banks
must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, at least two AUTO REFRESH cycles must be performed. After the
AUTO REFRESH cycles are complete, the SDRAM is ready for mode register program-
ming. Because the mode register will power up in an unknown state, it must be loaded
prior to applying any operational command. If desired, the two AUTO REFRESH com-
mands can be issued after the LMR command.
The recommended power-up sequence for SDRAM:
10. Issue an AUTO REFRESH command.
11. Wait at least
12. The SDRAM is now ready for mode register programming. Because the mode regis-
13. Wait at least
1. Simultaneously apply power to V
2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTL-
3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within tim-
4. Wait at least 100μs prior to issuing any command other than a COMMAND INHIB-
5. Starting at some point during this 100μs period, bring CKE HIGH. Continuing at
6. Perform a PRECHARGE ALL command.
7. Wait at least
8. Issue an AUTO REFRESH command.
9. Wait at least
compatible.
ing constraints specified for the clock pin.
IT or NOP.
least through the end of this period, 1 or more COMMAND INHIBIT or NOP com-
mands must be applied.
given. All banks will complete their precharge, thereby placing the device in the all
banks idle state.
mands are allowed.
mands are allowed.
ter will power up in an unknown state, it should be loaded with desired bit values
prior to applying any operational command. Using the LMR command, program
the mode register. The mode register is programmed via the MODE REGISTER
SET command with BA1 = 0, BA0 = 0 and retains the stored information until it is
programmed again or the device loses power. Not programming the mode register
upon initialization will result in default settings which may not be desired. Out-
puts are guaranteed High-Z after the LMR command is issued. Outputs should be
High-Z already before the LMR command is issued.
lowed.
DD
and V
t
t
t
t
RP time; during this time NOPs or DESELECT commands must be
RFC time, during which only NOPs or COMMAND INHIBIT com-
RFC time, during which only NOPs or COMMAND INHIBIT com-
MRD time, during which only NOP or DESELECT commands are al-
DDQ
(simultaneously) and the clock is stable (stable clock is defined
43
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
and V
DDQ
.
256Mb: x4, x8, x16 SDRAM
© 1999 Micron Technology, Inc. All rights reserved.
Initialization