MT48LC16M16A2P-75 IT:D TR Micron Technology Inc, MT48LC16M16A2P-75 IT:D TR Datasheet - Page 53
![DRAM Chip SDRAM 256M-Bit 16Mx16 3.3V 54-Pin TSOP-II T/R](/photos/7/22/72261/557-54-tsop_sml.jpg)
MT48LC16M16A2P-75 IT:D TR
Manufacturer Part Number
MT48LC16M16A2P-75 IT:D TR
Description
DRAM Chip SDRAM 256M-Bit 16Mx16 3.3V 54-Pin TSOP-II T/R
Manufacturer
Micron Technology Inc
Type
SDRAMr
Specifications of MT48LC16M16A2P-75 IT:D TR
Density
256 Mb
Maximum Clock Rate
133 MHz
Package
54TSOP-II
Address Bus Width
15 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
6|5.4 ns
Operating Temperature
-40 to 85 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
256M (16Mx16)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
54-TSOP II
Organization
16Mx16
Address Bus
15b
Access Time (max)
6/5.4ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
135mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
557-1058-2
Figure 21: Consecutive READ Bursts
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Note:
Command
Command
Address
Address
1. Each READ command can be issued to any bank. DQM is LOW.
CLK
CLK
DQ
DQ
T0
T0
Bank,
READ
READ
Col n
Bank,
Col n
CL = 2
CL = 3
T1
T1
NOP
NOP
53
T2
T2
NOP
NOP
D
OUT
n
T3
T3
NOP
NOP
Micron Technology, Inc. reserves the right to change products or specifications without notice.
D
D
n + 1
OUT
OUT
READ
T4
READ
T4
Bank,
Bank,
Col b
Col b
X = 1 cycle
D
n + 2
D
Transitioning data
OUT
OUT
256Mb: x4, x8, x16 SDRAM
X = 2 cycles
T5
T5
NOP
NOP
D
D
n + 3
OUT
OUT
© 1999 Micron Technology, Inc. All rights reserved.
T6
T6
NOP
NOP
READ Operation
D
D
OUT
OUT
b
Don’t Care
T7
NOP
D
OUT