MT46H8M32LFB5-6 IT:H Micron Technology Inc, MT46H8M32LFB5-6 IT:H Datasheet - Page 65

DRAM Chip DDR SDRAM 256M-Bit 8Mx32 1.8V 90-Pin VFBGA Tray

MT46H8M32LFB5-6 IT:H

Manufacturer Part Number
MT46H8M32LFB5-6 IT:H
Description
DRAM Chip DDR SDRAM 256M-Bit 8Mx32 1.8V 90-Pin VFBGA Tray
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet

Specifications of MT46H8M32LFB5-6 IT:H

Density
256 Mb
Maximum Clock Rate
166 MHz
Package
90VFBGA
Address Bus Width
14 Bit
Operating Supply Voltage
1.8 V
Maximum Random Access Time
6.5|5 ns
Operating Temperature
-40 to 85 °C
Organization
8Mx32
Address Bus
14b
Access Time (max)
6.5/5ns
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
120mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Compliant
Figure 28: READ-to-PRECHARGE
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN
Command
Command
Address
Address
DQ4
DQS
DQS
DQ
CK#
CK#
CK
CK
4
Notes:
Banka,
Col n
Banka,
Col n
READ
READ
T0
T0
1. BL = 4, or an interrupted burst of 8 or 16.
2. PRE = PRECHARGE command.
3. ACT = ACTIVE command.
4. D
5. Shown with nominal
6. READ-to-PRECHARGE equals 2 clocks, which enables 2 data pairs of data-out.
7. A READ command with auto precharge enabled, provided
1
1
cause a precharge to be performed at x number of clock cycles after the READ com-
mand, where x = BL/2.
OUT
n = data-out from column n.
CL = 2
NOP
NOP
T1
T1
CL = 3
T1n
T1n
D
(a or all)
(a or all)
t
Bank a,
Bank a,
AC,
OUT
T2
T2
PRE
PRE
t
2
65
2
DQSCK, and
D
T2n
T2n
OUT
256Mb: x16, x32 Mobile LPDDR SDRAM
D
OUT
Micron Technology, Inc. reserves the right to change products or specifications without notice.
D
T3
NOP
T3
NOP
OUT
t
DQSQ.
D
Don’t Care
OUT
T3n
t
t
T3n
D
RP
RP
OUT
D
OUT
T4
T4
NOP
NOP
D
OUT
t
RAS (MIN) is met, would
Transitioning Data
©2008 Micron Technology, Inc. All rights reserved.
READ Operation
Bank a,
Bank a,
T5
T5
ACT
Row
ACT
Row
3
3

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