MT46H8M32LFB5-6 IT:H Micron Technology Inc, MT46H8M32LFB5-6 IT:H Datasheet - Page 44

• Manufacturer Part Number: MT46H8M32LFB5-6 IT:H
• Description: DRAM Chip DDR SDRAM 256M-Bit 8Mx32 1.8V 90-Pin VFBGA Tray
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H8M32LFB5-6 IT:H

• Density: 256 Mb
• Maximum Clock Rate: 166 MHz
• Package: 90VFBGA
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 1.8 V
• Maximum Random Access Time: 6.5|5 ns
• Operating Temperature: -40 to 85 °C
• Organization: 8Mx32
• Address Bus: 14b
• Access Time (max): 6.5/5ns
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 120mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Table 17: Truth Table – CKE
Notes 1–4 apply to all parameters in this table
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN
Current State
Active power-down
Deep power-down
Precharge power-down
Self refresh
Active power-down
Deep power-down
Precharge power-down
Self refresh
Bank(s) active
All banks idle
All banks idle
All banks idle
Notes:
CKE
1. CKE
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMAND
4. All states and sequences not shown are illegal or reserved.
5. DESELECT or NOP commands should be issued on each clock edge occurring during the
6. After exiting deep power-down mode, a full DRAM initialization sequence is required.
7. The clock must toggle at least two times during the
H
H
H
H
H
H
L
L
L
L
L
L
L
L
n - 1
ous clock edge.
MAND
t
XP or
n
CKE
is the logic state of CKE at clock edge n; CKE
H
H
H
H
H
H
L
L
L
L
L
L
L
L
t
n
XSR period.
.
n
n
is the command registered at clock edge n, and ACTION
See Table 16 (page 41)
See Table 16 (page 41)
BURST TERMINATE
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
AUTO REFRESH
COMMAND
X
X
X
X
44
256Mb: x16, x32 Mobile LPDDR SDRAM
n
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Maintain precharge power-down
Precharge power-down entry
Maintain active power-down
Maintain deep power-down
Exit precharge power-down
Active power-down entry
Deep power-down entry
Exit active power-down
Exit deep power-down
n - 1
Maintain self refresh
Self refresh entry
t
XSR period.
Exit self refresh
was the state of CKE at the previ-
ACTION
©2008 Micron Technology, Inc. All rights reserved.
n
n
is a result of COM-
Truth Tables
Notes
5, 7
5
6