WM8196SCDS Wolfson Microelectronics, WM8196SCDS Datasheet - Page 14

• Manufacturer Part Number: WM8196SCDS
• Description: Video ICs 16-Bit 12MSPS 3-Channel AFE
• Manufacturer: Wolfson Microelectronics
• Type: CCD/CISr

Specifications of WM8196SCDS

• Operating Supply Voltage: 3.3 V or 5 V
• Supply Current: 60 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: SSOP-28
• Conversion Rate: 12000 KSPS
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Channels: 3
• Resolution: 16 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8196
CDS/NON-CDS PROCESSING
w
Figure 9 Reset Level Clamping and CDS Circuitry
If auto-cycling is not required, RLC can be selected by pin RLC/ACYC. Figure 10 illustrates control of
RLC for a typical CCD waveform, with CL applied during the reset period.
The input signal applied to the RLC/ACYC pin is sampled on the positive edge of MCLK that occurs
during each VSMP pulse. The sampled level, high (or low) controls the presence (or absence) of the
internal CL pulse on the next reset level. The position of CL can be adjusted by using control bits
CDSREF[1:0] (Figure 11).
If auto-cycling is required, pin RLC/ACYC is no longer available for this function and control bit
RLCINT determines whether clamping is applied.
Figure 10 Relationship of RLC Pin, MCLK and VSMP to Internal Clamp Pulse, CL
The VRLC/VBIAS pin can be driven internally by a 4-bit DAC (RLCDAC) by writing to control bits
RLCV[3:0]. The RLCDAC range and step size may be increased by writing to control bit
RLCDACRNG. Alternatively, the VRLC/VBIAS pin can be driven externally by writing to control bit
VRLCEXT to disable the RLCDAC and then applying a d.c. voltage to the pin.
For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel
common mode noise. For CDS operation, the video level is processed with respect to the video reset
level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must
be set to 1 (default), this sets switch 2 into the position shown in Figure 9 and causes the signal
reference to come from the video reset level. The time at which the reset level is sampled, by clock
R
(CDSREF = 01)
INPUT VIDEO
s
/CL, is adjustable by programming control bits CDSREF[1:0], as shown in Figure 11.
ACYC/RLC
or RLCINT
MCLK
VSMP
EXTERNAL VRLC
CL
1
C
RGB
IN
VBIAS
VRLC/
RINP
Programmable Delay
X
1
RLC
CL
2
RLC/ACYC
X
TIMING CONTROL
VRLCEXT
RLC DAC
4-BIT
RLC on this Pixel
S/H
R
S
CDS
CDS
MCLK
0
RGB
S/H
V
S
VSMP
X
INPUT SAMPLING
BLOCK FOR RED
CHANNEL
+
-
+
PD Rev 4.3 March 2007
FROM CONTROL
INTERFACE
TO OFFSET DAC
FROM CONTROL
INTERFACE
X
No RLC on this Pixel
Production Data
RGB
0
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