WM8196SCDS Wolfson Microelectronics, WM8196SCDS Datasheet
WM8196SCDS
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WM8196SCDS Summary of contents
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... U BIT X ADC I/P SIGNAL POLARITY ADJUST + I/P SIGNAL POLARITY CONFIGURABLE ADJUST SERIAL CONTROL INTERFACE DGND Production Data, March 2007, Rev 4.3 Copyright ©2007 Wolfson Microelectronics plc OEB OP[0] OP[1] OP[2] OP[3] OP[4] OP[5] OP[6] OP[7]/SDO SEN SCK SDI RLC/ACYC ...
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WM8196 DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................5 THERMAL PERFORMANCE .................................................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6 INPUT VIDEO SAMPLING ............................................................................................. 8 OUTPUT ...
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... RINP 1 AGND2 2 DVDD1 3 OEB 4 VSMP 5 RLC/ACYC 6 MCLK 7 DGND 8 SEN 9 DVDD2 10 SDI 11 SCK 12 OP[0] 13 OP[1] 14 ORDERING INFORMATION TEMPERATURE DEVICE WM8196SCDS WM8196SCDS Note: Reel quantity = 2,000 w 28 GINP 27 BINP 26 VRLC/VBIAS 25 VRX 24 VRT 23 VRB 22 AGND1 21 AVDD 20 OP[7]/SDO 19 OP[6] 18 OP[5] 17 OP[4] 16 OP[3] 15 OP[2] PACKAGE ...
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WM8196 PIN DESCRIPTION PIN NAME TYPE 1 RINP Analogue input 2 AGND2 Supply 3 DVDD1 Supply 4 OEB Digital input 5 VSMP Digital input 6 RLC/ACYC Digital input 7 MCLK Digital input 8 DGND Supply 9 SEN Digital input 10 ...
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WM8196 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics ...
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WM8196 ELECTRICAL CHARACTERISTICS Test Conditions AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, T PARAMETER Overall System Specification (including 16-bit ADC, PGA, Offset and CDS functions) Conversion Rate Full-scale input voltage range (see Note 1) ...
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WM8196 Test Conditions AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, T PARAMETER Programmable Gain Amplifier Resolution Gain Max gain, each channel Min gain, each channel Gain error, each channel Analogue to Digital Converter Resolution ...
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WM8196 INPUT VIDEO SAMPLING t MCLK t VSMPSU VSMP INPUT VIDEO Figure 1 Input Video Timing Note: 1. See Page 14 (Programmable VSMP Detect Circuit) for video sampling description. Test Conditions AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND ...
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WM8196 OEB OP[7:0] Hi-Z Figure 3 Output Data Enable Timing Test Conditions AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, T PARAMETER Output propagation delay Output enable time Output disable time MCLK t ACYCSU RLC/ACYC ...
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WM8196 SERIAL INTERFACE t SPER SCK t t SSU SH SDI SEN SDO Figure 5 Serial Interface Timing Test Conditions AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, T PARAMETER SCK period SCK high SCK ...
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WM8196 INTERNAL POWER ON RESET CIRCUIT Figure 6 Internal Power On Reset Circuit Schematic The WM8196 includes an internal Power-On-Reset Circuit, as shown in Figure 6, which is used to reset the digital logic into a default state after power ...
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WM8196 Figure 8 Typical Power up Sequence where DVDD1 is Powered before AVDD Figure 8 shows a typical power-up sequence where DVDD1 is powered up first assumed that DVDD1 is already up to specified operating voltage. When AVDD ...
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WM8196 DEVICE DESCRIPTION INTRODUCTION A block diagram of the device showing the signal path is presented on Page 1. The WM8196 samples up to three inputs (RINP, GINP and BINP) simultaneously. The device then processes the sampled video signal with ...
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WM8196 EXTERNAL VRLC Figure 9 Reset Level Clamping and CDS Circuitry If auto-cycling is not required, RLC can be selected by pin RLC/ACYC. Figure 10 illustrates control of RLC for a typical CCD waveform, with CL applied during the reset ...
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WM8196 R /CL (CDSREF = 00 /CL (CDSREF = 01 /CL (CDSREF = 10 /CL (CDSREF = 11) S Figure 11 Reset Sample and Clamp Timing For CIS type sensor signals, non-CDS processing is ...
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WM8196 ADC INPUT BLACK LEVEL ADJUST The output from the PGA should be offset to match the full-scale range of the ADC (3V). For negative-going input video signals, a black level (zero differential) output from the PGA should be offset ...
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WM8196 If RLCEXT = RLCSTEP OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST The resultant signal V PGA NODE: GAIN ADJUST The signal is then multiplied by the PGA gain, ADC BLOCK: ANALOGUE-DIGITAL CONVERSION The analogue signal is then ...
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WM8196 OUTPUT FORMAT 8+8-bit multiplexed 4+4+4+4-bit (nibble) Table 2 Details of Output Data Shown in Figure 15 and Figure 16. CONTROL INTERFACE The internal control registers are programmable via the serial digital control interface. The register contents can be read ...
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WM8196 SCK SDI SEN SDO/ OP[7] OEB Figure 18 Serial Interface Register Read-back TIMING REQUIREMENTS To use this device a master clock (MCLK 24MHz and a per-pixel synchronisation clock (VSMP 12MHz are required. These ...
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WM8196 (VDEL = 000) INTVSMP (VDEL = 001) INTVSMP (VDEL = 010) INTVSMP (VDEL = 011) INTVSMP (VDEL = 100) INTVSMP (VDEL = 101) INTVSMP (VDEL = 110) INTVSMP (VDEL = 111) INTVSMP (VDEL = 000) INTVSMP (VDEL = 001) ...
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WM8196 LINE-BY-LINE OPERATION Certain linear sensors (e.g. Contact Image Sensors) give colour output on a line-by-line basis. i.e. a full line of red pixels followed by a line of green pixels followed by a line of blue pixels. In order ...
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WM8196 OPERATING MODES Table 5 summarises the most commonly used modes, the clock waveforms required and the register contents required for CDS and non-CDS operation. MODE DESCRIPTION CDS AVAILABLE 1 Colour Yes Pixel-by-Pixel 2 Monochrome/ Yes Colour Line-by-Line 3 Fast ...
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WM8196 OPERATING MODE TIMING DIAGRAMS The following diagrams show 8-bit multiplexed output data and MCLK, VSMP and input video requirements for operation of the most commonly used modes as shown in Table 5. The diagrams are identical for both CDS ...
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WM8196 Figure 23 Mode 3 Operation Figure 24 Mode 4 Operation w Production Data PD Rev 4.3 March 2007 24 ...
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WM8196 16.5 MCLK PERIODS MCLK VSMP INPUT VIDEO OP[7: (DEL = 00) OP[7: (DEL = 01) ...
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WM8196 DEVICE CONFIGURATION REGISTER MAP The following table describes the location of each control bit used to determine the operation of the WM8196. The register map is programmed by writing the required codes to the appropriate addresses via the serial ...
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WM8196 REGISTER MAP DESCRIPTION The following table describes the function of each of the control bits shown in Table 6. REGISTER BIT BIT NO NAME(S) Setup 0 EN Register 1 1 CDS 2 MONO 3 SELPD 5:4 PGAFS[1:0] 6 MODE4 ...
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WM8196 REGISTER BIT BIT NO NAME(S) Setup 0 LINEBYLINE Register 4 1 ACYCNRLC 2 FME 3 RLCINT 5:4 INTM[1:0] 7:6 FM[1:0] Setup 0 VSMPDET Register 5 3:1 VDEL[2:0] 4 POSNNEG 7:5 Reserved Setup 3:0 SELDIS[3:0] Register 6 7:4 Reserved w ...
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WM8196 REGISTER BIT BIT NO NAME(S) Offset DAC 7:0 DAC[7:0] (Red) Offset DAC 7:0 DAC[7:0] (Green) Offset DAC 7:0 DAC[7:0] (Blue) Offset DAC 7:0 DAC[7:0] (RGB) PGA gain 7:0 PGA[7:0] (Red) PGA gain 7:0 PGA[7:0] (Green) PGA gain 7:0 PGA[7:0] ...
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WM8196 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS DVDD1 DVDD2 C1 C2 AVDD DGND AGND Video Inputs AGND Timing Signals Interface Controls NOTES: 1. C1-9 should be fitted as close to WM8196 as possible. 2. AGND and DGND should be connected as ...
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WM8196 PACKAGE DIMENSIONS DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm Dimensions Symbols (mm) MIN NOM A ----- A 0. 1.65 1. 0.22 c 0.09 D 9.90 10.20 ...
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... WM8196 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...