MAX9880AEWM+T Maxim Integrated Products, MAX9880AEWM+T Datasheet - Page 60

• Manufacturer Part Number: MAX9880AEWM+T
• Description: CODECs Low-Power, High Perf ormance Dual I2S Ste
• Manufacturer: Maxim Integrated Products

Specifications of MAX9880AEWM+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Low-Power, High-Performance
Dual I
Figure 16. Acknowledge
Figure 17. Writing 1 Byte of Data
The slave address is defined as the seven most signifi-
cant bits (MSBs) followed by the read/write bit. For the
MAX9880A, the seven most significant bits are
0010000. Setting the read/write bit to 1 (slave address
= 0x21) configures the MAX9880A for read mode.
Setting the read/write bit to 0 (slave address = 0x20)
configures the MAX9880A for write mode. The address
is the first byte of information sent to the MAX9880A
after the START condition.
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9880A uses to handshake receipt each byte of
data when in write mode (see Figure 16). The
MAX9880A pulls down SDA during the entire master-
generated 9th clock pulse if the previous byte is suc-
cessfully received. Monitoring ACK allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a sys-
tem fault has occurred. In the event of an unsuccessful
data transfer, the bus master retries communication.
60
S
______________________________________________________________________________________
2
SLAVE ADDRESS
ACKNOWLEDGE FROM MAX9880A
S Stereo Audio Codec
SCL
SDA
CONDITION
R/W
START
0
A
Slave Address
Acknowledge
1
ACKNOWLEDGE FROM MAX9880A
REGISTER ADDRESS
2
NOT ACKNOWLEDGE
The master pulls down SDA during the 9th clock cycle
to acknowledge receipt of data when the MAX9880A is
in read mode. An acknowledge is sent by the master
after each read byte to allow data transfer to continue.
A not acknowledge is sent when the master reads the
final byte of data from the MAX9880A, followed by a
STOP condition.
A write to the MAX9880A includes transmission of a
START condition, the slave address with the R/W bit set
to 0, 1 byte of data to configure the internal register
address pointer, 1 or more bytes of data, and a STOP
condition. Figure 17 illustrates the proper frame format
for writing 1 byte of data to the MAX9880A. Figure 18
illustrates the frame format for writing n bytes of data to
the MAX9880A.
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the MAX9880A.
The MAX9880A acknowledges receipt of the address
byte during the master-generated 9th SCL pulse.
ACKNOWLEDGE
ACKNOWLEDGMENT
CLOCK PULSE FOR
A
9
B7
B6
ACKNOWLEDGE FROM MAX9880A
B5
DATA BYTE
B4
1 BYTE
B3
B2
REGISTER ADDRESS POINTER
Write Data Format
AUTOINCREMENT INTERNAL
B1
B0
A
P