MAX9880AEWM+T Maxim Integrated Products, MAX9880AEWM+T Datasheet
MAX9880AEWM+T
Specifications of MAX9880AEWM+T
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MAX9880AEWM+T Summary of contents
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... Applications Cellular Phones Tablet PCs Portable Gaming Devices Portable Multimedia Players SPI is a trademark of Motorola, Inc. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Low-Power, High-Performance 2 Dual I S Stereo Audio Codec o 1 ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec ABSOLUTE MAXIMUM RATINGS (Voltages with respect to AGND.) DVDD, AVDD, PVDD ................................................-0.3V to +2V DVDDS1, JACKSNS, MICVDD ..............................-0.3V to +3.6V DGND, PGND........................................................-0.1V to +0.1V PREG, REF, REG ....................................-0. MICBIAS ...
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ELECTRICAL CHARACTERISTICS (continued AVDD PVDD MICVDD DVDD ferential modes 2.2µF, C REF MICBIAS AV = 0dB 0dB 13MHz, T VOL LO MCLK PARAMETER SYMBOL DAC ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec ELECTRICAL CHARACTERISTICS (continued AVDD PVDD MICVDD DVDD ferential modes 2.2µF, C REF MICBIAS AV = 0dB 0dB, f ...
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ELECTRICAL CHARACTERISTICS (continued AVDD PVDD MICVDD DVDD ferential modes 2.2µF, C REF MICBIAS AV = 0dB 0dB 13MHz, T VOL LO MCLK PARAMETER SYMBOL Total ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec ELECTRICAL CHARACTERISTICS (continued AVDD PVDD MICVDD DVDD ferential modes 2.2µF, C REF MICBIAS AV = 0dB 0dB, f ...
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ELECTRICAL CHARACTERISTICS (continued AVDD PVDD MICVDD DVDD ferential modes 2.2µF, C REF MICBIAS AV = 0dB 0dB 13MHz, T VOL LO MCLK PARAMETER SYMBOL Power-Supply ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec ELECTRICAL CHARACTERISTICS (continued AVDD PVDD MICVDD DVDD ferential modes 2.2µF, C REF MICBIAS AV = 0dB 0dB, f ...
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ELECTRICAL CHARACTERISTICS (continued AVDD PVDD MICVDD DVDD ferential modes 2.2µF, C REF MICBIAS AV = 0dB 0dB 13MHz, T VOL LO MCLK PARAMETER SYMBOL Line ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec ELECTRICAL CHARACTERISTICS (continued AVDD PVDD MICVDD DVDD ferential modes 2.2µF, C REF MICBIAS AV = 0dB 0dB, f ...
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ELECTRICAL CHARACTERISTICS (continued AVDD PVDD MICVDD DVDD ferential modes 2.2µF, C REF MICBIAS AV = 0dB 0dB 13MHz, T VOL LO MCLK PARAMETER SYMBOL DIGITAL ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec ELECTRICAL CHARACTERISTICS (continued AVDD PVDD MICVDD DVDD ferential modes 2.2µF, C REF MICBIAS AV = 0dB 0dB, f ...
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ELECTRICAL CHARACTERISTICS (continued AVDD PVDD MICVDD DVDD ferential modes 2.2µF, C REF MICBIAS AV = 0dB 0dB 13MHz, T VOL LO MCLK PARAMETER SYMBOL TDM ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec ELECTRICAL CHARACTERISTICS (continued AVDD PVDD MICVDD DVDD ferential modes 2.2µF, C REF MICBIAS AV = 0dB 0dB, f ...
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AVDD PVDD MICVDD DVDD C = 2.2µ REF MICBIAS PREG REG AV = 0dB 13MHz, differential output, unless otherwise noted.) LO MCLK TOTAL HARMONIC ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec ( AVDD PVDD MICVDD DVDD C = 2.2µ REF MICBIAS PREG REG AV = 0dB 13MHz, ...
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AVDD PVDD MICVDD DVDD C = 2.2µ REF MICBIAS PREG REG AV = 0dB 13MHz, differential output, unless otherwise noted.) LO MCLK TOTAL HARMONIC ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec ( AVDD PVDD MICVDD DVDD C = 2.2µ REF MICBIAS PREG REG AV = 0dB 13MHz, ...
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AVDD PVDD MICVDD DVDD C = 2.2µ REF MICBIAS PREG REG AV = 0dB 13MHz, differential output, unless otherwise noted.) LO MCLK POWER-SUPPLY REJECTION ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec ( AVDD PVDD MICVDD DVDD C = 2.2µ REF MICBIAS PREG REG AV = 0dB 13MHz, ...
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AVDD PVDD MICVDD DVDD C = 2.2µ REF MICBIAS PREG REG AV = 0dB 13MHz, differential output, unless otherwise noted.) LO MCLK WIDEBAND FFT, ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec ( AVDD PVDD MICVDD DVDD C = 2.2µ REF MICBIAS PREG REG AV = 0dB 13MHz, ...
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Low-Power, High-Performance TOP VIEW (BUMP SIDE DOWN DGND DVDD SDA/DIN SCL/SCLK B SDINS2 LRCLKS2 BCLKS2 C MCLK SDOUTS2 SDINS1 D LRCLKS1 BCLKS1 PVDD E SDOUTS1 DVDDS1 PVDD F TOP VIEW ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec PIN NAME TQFN-EP WLP 1 B2 SDA/DIN 2 B3 SCL/SCLK DOUT 7 A5 MODE AVDD 10 B6 ...
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PIN NAME TQFN-EP WLP 23 E8 LINL 24 F8 LINR 25 F7 LOUTR 26 E7 LOUTL 27 E6, F6 PGND 29 E5 ROUTP 30 F5 ROUTN 31 F4 LOUTN 32 E4 LOUTP 34 E3, F3 PVDD 36 F2 DVDDS1 37 ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec Detailed Description The MAX9880A is a low-power stereo audio codec designed for portable applications requiring minimum power consumption. The stereo playback path accepts digital audio through flexible digital audio interfaces compatible ...
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Table 1. Register Map (continued) REGISTER B7 DAI1 CLOCK CONTROL Stereo Audio Clock Control High PLL1 Stereo Audio Clock Control Low DAI1 CONFIGURATION Interface Mode A MAS1 Interface Mode B DL1 Time-Division Multiplex SLOTL1 DAI2 CLOCK CONTROL Stereo Audio Clock ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec Table 1. Register Map (continued) REGISTER B7 POWER MANAGEMENT Enable LNLEN System Shutdown REVISION ID Revision ID * Reserved. Grayed boxes = Not used. Note: Register addresses listed are for I ...
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Table 3. Status Register Bits BITS Clip Detect Flag. Indicates that a signal has become clipped in the ADC or DAC. To resolve a clip condition in CLD the signal path, the DAC gain settings and analog input gain settings ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec Hardware Interrupts Hardware interrupts are reported on the open-drain IRQ pin. When an interrupt occurs, IRQ remains low until the interrupt is serviced by reading the status register 0x00. Table 4. ...
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Table 5. System and Audio Clock Registers (continued) BITS MCLK Prescaler. Divides MCLK down to generate a PCLK between 10MHz and 20MHz Disable clock for low-power shutdown. PSCLK 01 = Select if MCLK is between 10MHz and 20MHz. ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec Table 6. Common NI Values LRCLK (kHz) 8 11.025 10 13A9 1B18 11 11E0 18A2 11.2896 116A 1800 12 1062 1694 PCLK (MHz): 12.288 1000 160D (Note: Any 13 F20 14D8 ...
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Table 7. Digital Audio Interface Registers REGISTER B7 DAI1 CONFIGURATION Interface Mode A MAS1 Interface Mode B DL1 Time-Division Multiplex SLOTL1 DAI2 CONFIGURATION Interface Mode A MAS2 Interface Mode B DL2 Time-Division Multiplex SLOTL2 Grayed boxes = Not used. Note: ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec Table 7. Digital Audio Interface Registers (continued) BITS TDM Mode Select TDM1 Enables time-division multiplex mode and configures the audio interface to accept PCM data Disables time-division ...
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Table 7. Digital Audio Interface Registers (continued) BITS BCLK Select. Configures BCLK when operating in master mode. BSEL has no effect in slave mode. Set BSEL = 010, unless sharing the bus with multiple devices. BSEL BSEL1/2 TDM Slot Select. ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec AUDIO MASTER MODES: LEFT JUSTIFIED: TDM = 0, WCI = 0, BCI = 0, DLY = 0, SLOTDLY = 0 7ns (typ) LRCLK RELATIVE TO PCLK (SEE NOTE) D15 D14 D13 ...
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AUDIO SLAVE MODES: LEFT JUSTIFIED: TDM = 0, WCI = 0, BCI = 0, DLY = 0, SLOTDLY = 0 LRCLK 20ns (min) D15 D14 D13 D12 D11 D10 SDOUT ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec VOICE (TDM/PCM) MASTER MODES: TDM = 1, BCI = 0, HIZOFF = 0, SLOTDLY = 0, SLOT = 00, DLY = 0 7ns (typ) LRCLK 200ns SDOUT L15 L14 L13 L12 ...
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VOICE (TDM/PCM) SLAVE MODES: TDM = 1, BCI = 0, HIZOFF = 0, SLOTDLY = 0, SLOT = 00, DLY = 0 LRCLK 20ns SDOUT L15 L14 L13 L12 L11 L10 ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec The MAX9880A incorporates both IIR (voice) and FIR (audio) digital filters to accomodate a wide range of audio sources. The IIR fiilters provide over 70dB of Table 9. Digital Filtering Register ...
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Table 11. SPDM Output Registers REGISTER B7 Configuration SPDMCLK Input Grayed boxes = Not used. Note: Register addresses listed are for I accessible through SPI. The MAX9880A supports stereo PDM outputs. The PDM signals consist of PDM data outputs (SPDMDATA) ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec Digital Gain Control The MAX9880A includes gain adjustment for the play- back and record paths. Independent gain adjustment is Table 12. Digital Gain Registers REGISTER B7 LEVEL CONTROL Sidetone DSTS Stereo ...
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Table 12. Digital Gain Registers (continued) BITS DAC Mute Enable SDACM mute VDACM 1 = Mute DAC Gain 00 = 0dB 01 = +6dB VDACG 10 = +12dB 11 = +18dB Note: VDACG is only used when ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec The MAX9880A include one pair of single-ended line inputs. When enabled the line inputs connect directly to the headphone amplifier and line outputs and can be optionally connected to the ADC ...
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Table 14. Playback Volume Registers (continued) BITS Left/Right Playback Volume. VOLL and VOLR control the playback volume for both the DAC and line input audio signals. SETTING 0x00 0x01 0x02 0x03 0x04 0x05 0x06 VOLL/VOLR 0x07 0x08 0x09 0x0A 0x0B ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec Microphone Inputs Two differential microphone inputs and a low noise 1.5V microphone bias for powering the microphones are provided by the MAX9880A. In typical applications, the left microphone records a voice ...
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Table 16. Microphone Input Registers (continued) BITS Left/Right Microphone Programmable Gain Amplifier SETTING 0x00 0x01 0x02 0x03 PGAML/ 0x04 PGAMR 0x05 0x06 0x07 0x08 0x09 0x0A The MAX9880A includes two 18-bit ADCs. The first ADC is used to record left-channel ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec Offset Calibration Procedure Perform before the first DC measurement is taken after applying power to the MAX9880A. 1) Enable the AUX input (AUXEN = 1). 2) Enable the offset calibration (AUXCAL ...
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Table 18. ADC Input Register REGISTER B7 Input MXINL Note: Register addresses listed are for I accessible through SPI. BITS Left/Right ADC Audio Input Mixer input selected 01 = Left/right analog microphone 10 = Left/right line input ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec Digital Microphone Input The MAX9880A can accept audio from up to two digi- tal microphones. When using digital microphones, the left analog microphone input is retasked as a digital DIGMICCLK t ...
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Mode Configuration The MAX9880A includes circuitry to minimize click-and- pop during volume changes, detect headsets, and con- figure the headphone amplifier mode. Both volume slewing and zero-crossing detection are included to ensure click-and-pop free volume transitions. Headset Detection Overview The ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec Figure 8. Typical Configuration for Headset Detection Table 22. Debounce Time JDEB DEBOUNCE (ms 100 11 200 Configures the JDET debounce time for changes to JKSNS[1:0] according to ...
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Table 23. Headset Detect Configuration SHDN MICBIAS JDWK 0 — — — — — — — — ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec The MAX9880A’s headphone amplifier supports differen- tial, single-ended, and capacitorless output modes, as shown in Figure 9. In each mode, the amplifier can be configured for stereo or mono operation. The ...
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Table 24. Mode Configuration Register (continued) BITS Headphone Amplifier Mode HPMODE Note: In mono operation, the right amplifier is disabled. Jack-Detection Enable SHDN = 0: Sleep Mode. Enables pullups on JACKSNS/AUX to detect jack insertion. JDETEN SHDN = 1: Normal ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec Table 25. Power Management Register REGISTER B7 Enable LNLEN System Shutdown Grayed boxes = Not used. Note: Register addresses listed are for I accessible through SPI. BITS Left-Line Input Enable. Enables ...
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CSS SCLK t CH DIN t DH DOUT Figure 10. SPI Interface Timing Diagram CS SCLK DIN R/W ADDR9 HIGH-Z DOUT Figure 11. Writing 1 Byte of Data to the MAX9880A Serial Peripheral Interface ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec CS SCLK DIN R/W ADDR9 HIGH-Z DOUT Figure 12. Reading 1 Byte of Data from the MAX9880A CS SCLK DIN R/W ADDR9 HIGH-Z DOUT Figure 13. Reading n Bytes of Data ...
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SDA t SU,DAT t LOW t SCL HIGH t HD,STA t R START CONDITION Figure 14. 2-Wire Interface Timing Diagram SCL SDA Figure 15. START, STOP, and Repeated START Conditions sequence is framed by a START or repeated START condition, ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec START CONDITION SCL SDA Figure 16. Acknowledge ACKNOWLEDGE FROM MAX9880A S SLAVE ADDRESS 0 R/W Figure 17. Writing 1 Byte of Data The slave address is defined as the seven most ...
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The second byte transmitted from the master config- ures the MAX9880A’s internal register address pointer. The pointer tells the MAX9880A where to write the next byte of data. An acknowledge pulse is sent by the MAX9880A upon receipt of the ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec ACKNOWLEDGE FROM MAX9880A ACKNOWLEDGE FROM MAX9880A S SLAVE ADDRESS 0 A REGISTER ADDRESS R/W Figure 20. Reading n Bytes of Data Applications Information Proper layout and grounding are essential for optimum ...
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Table 29. Line Input Playback SEQUENCE 1 Set line input gain 2 Set volume 3 Set line output volume (if using) 4 Select headphone mode 5 Enable line outputs and line inputs as required 6 Enable MAX9880A 7 Enable external ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec Table 32. Voice Microphone Record SEQUENCE 1 Select voice filters 2 Set ADC level to 0dB 3 Configure microphone gain 4 Set line output volume (if using) 5 Configure ADC input ...
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Example of Register Settings for Music Playback and Voice Duplex Senarios f = 12.288MHz (master clock supplied to codec), MCLK 48kHz, standard I S format, codec in slave LRCLK Table 34. Music Playback SEQUENCE DESCRIPTION 1 = ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec PVDD PREG AVDD DVDD SDOUTS2 SDINS2 LRCLKS2 BCLKS2 SDOUTS1 SDINS1 LRCLKS1 BCLKS1 FREQ1 MCLK PSCLK SPDMCLK DOUT SDA/DIN CS SCL/SCLK MODE IRQ MICVDD DVDDS1 66 ______________________________________________________________________________________ Functional Diagram/Typical Operating Circuit MIX ...
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For the latest package outline information and land patterns (footprints www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per- ...
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Low-Power, High-Performance 2 Dual I S Stereo Audio Codec For the latest package outline information and land patterns (footprints www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may ...
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For the latest package outline information and land patterns (footprints www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per- ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 70 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2011 Maxim Integrated Products DESCRIPTION Maxim is a registered trademark of Maxim Integrated Products, Inc ...