MAX9880AEWM+T Maxim Integrated Products, MAX9880AEWM+T Datasheet - Page 41

• Manufacturer Part Number: MAX9880AEWM+T
• Description: CODECs Low-Power, High Perf ormance Dual I2S Ste
• Manufacturer: Maxim Integrated Products

Specifications of MAX9880AEWM+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 11. SPDM Output Registers
Figure 5. SPDM Timing Diagram
Grayed boxes = Not used.
Note: Register addresses listed are for I
accessible through SPI.
The MAX9880A supports stereo PDM outputs. The PDM
signals consist of PDM data outputs (SPDMDATA) and a
clock output (SPDMCLK). The mixer at the input to the
Configuration
Input
SPDML/SPDMR
MIXSPDML/
MIXSPDMR
SPDMCLK
SPDMCLK
SPDMDATA
REGISTER
BITS
LEFT CH
______________________________________________________________________________________
SPDM Clock Rate (SPDMCLK)
00 = SPDMCLK is set to PCLK/8.
01 = SPDMCLK is set to PCLK6.
10 = SPDMCLK is set to PCLK/4.
11 = Reserved
0 = Disables SPDM data.
1 = Enables SPDM data.
SPDM Input Mixers. Selects and mixes the audio source(s) for the SPDM output according to following
information.
t
DLY, DSD
B7
SPDMCLK
MIXSPDML/MIXSPDMR
B6
RIGHT CH
2
t
DLY, DSD
MIXSPDML
C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
1xxx
x1xx
xx1x
xxx1
Low-Power, High-Performance
SPDML
B5
Dual I
SPDMR
B4
LEFT CH
PDM modulators allows a mix/mux of the audio digital data
stream from the digital audio ports SDINS1 and SDINS2.
Figure 5 shows the SPDM interface timing diagram.
2
FUNCTION
S Stereo Audio Codec
B3
0
B2
0
MIXSPDMR
RIGHT CH
DAI1 right-channel data
DAI2 right-channel data
DAI1 left-channel data
DAI2 left-channel data
B1
0
SOURCE
B0
0
(SEE NOTE)
REGISTER
ADDRESS
0x12
0x13
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