MAX9880AEWM+T Maxim Integrated Products, MAX9880AEWM+T Datasheet - Page 25

• Manufacturer Part Number: MAX9880AEWM+T
• Description: CODECs Low-Power, High Perf ormance Dual I2S Ste
• Manufacturer: Maxim Integrated Products

Specifications of MAX9880AEWM+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TQFN-EP
23
24
25
26
27
29
30
31
32
34
36
37
38
39
40
41
42
43
44
45
46
47
—
PIN
E6, F6
E3, F3
WLP
D3
C1
C2
C3
B1
A1
E8
E7
E5
F5
F4
E4
F2
E1
E2
D1
D2
F8
F7
F1
—
______________________________________________________________________________________
SDOUTS1
LRCLKS1
SDOUTS2
LRCLKS2
DVDDS1
BCLKS1
BCLKS2
ROUTN
SDINS1
SDINS2
ROUTP
LOUTN
LOUTR
LOUTP
LOUTL
NAME
DGND
PGND
MCLK
DVDD
PVDD
LINR
LINL
EP
Low-Power, High-Performance
Left-Line Input. AC-couple analog audio signal to LINL with a 1µF capacitor.
Right-Line Input. AC-couple analog audio signal to LINR with a 1µF capacitor.
Right-Line Output
Left-Line Output
Headphone Power Ground
Positive Right-Channel Headphone Output. Connect directly to the load in
differential and capacitorless mode. AC-couple to the load in single-ended mode.
Negative Right-Channel Headphone Output. Unused in capacitorless and
single-ended mode.
Negative Left-Channel Headphone Output. Common headphone return in
capacitorless mode. Unused in single-ended mode.
Positive Left-Channel Headphone Output. Connect directly to the load in
differential and capacitorless mode. AC-couple to the load in single-ended mode.
Headphone Power Supply. Bypass to PGND with a 1µF capacitor.
S1 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1µF
capacitor.
S1 Digital Audio Serial-Data ADC Output
S1 Digital Audio Serial-Data DAC Input
S1 Digital Audio Left-Right Clock Input/Output. LRCLKS1 is the audio sample
rate clock and determines whether the audio data on SDINS1 is routed to the left
or right channel. In TDM mode, LRCLKS1 is a frame sync pulse. LRCLKS1 is an
input when the MAX9880A is in slave mode and an output when in master
mode.
S1 Digital Audio Bit Clock Input/Output. BCLKS1 is an input when the
MAX9880A is in slave mode and an output when in master mode.
Master Clock Input. Acceptable input frequency range: 10MHz to 60MHz.
S2 Digital Audio Serial-Data ADC Output
S2 Digital Audio Serial-Data DAC Input
S2 Digital Audio Left-Right Clock Input/Output. LRCLKS2 is the audio sample
rate clock and determines whether the audio data on SDINS2 is routed to the left
or right channel. In TDM mode, LRCLKS2 is a frame sync pulse. LRCLKS2 is an
input when the MAX9880A is in slave mode and an output when in master
mode.
S2 Digital Audio Bit Clock Input/Output. BCLKS2 is an input when the
MAX9880A is in slave mode and an output when in master mode.
Digital Power Supply. Supply for the digital core and I
DGND with a 1.0µF capacitor.
Digital Ground
Exposed Pad. Connect the exposed thermal pad to AGND.
Dual I
2
S Stereo Audio Codec
Pin Description (continued)
FUNCTION
2
C/SPI interface. Bypass to
25