MAX9880AEWM+T Maxim Integrated Products, MAX9880AEWM+T Datasheet - Page 51

• Manufacturer Part Number: MAX9880AEWM+T
• Description: CODECs Low-Power, High Perf ormance Dual I2S Ste
• Manufacturer: Maxim Integrated Products

Specifications of MAX9880AEWM+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX9880A includes circuitry to minimize click-and-
pop during volume changes, detect headsets, and con-
figure the headphone amplifier mode. Both volume
slewing and zero-crossing detection are included to
ensure click-and-pop free volume transitions.
The MAX9880A contains headset detect circuitry that is
capable of detecting the insertion or removal of a plug
1 = Jack configuration has changed.
0 = No change in jack configuration.
JDET reports changes in JKSNS[1:0]. Changes to
JKSNS[1:0] are debounced before setting JDET. The
debounce period is programmable using the JDEB bits.
Jack status register 0x01 is a read-only register that reports
the status of the jack-detect circuitry when enabled.
JKSNS[1:0] reports the status of the JACKSNS pin
when JDETEN = 1. JKSNS[1:0] should be interpreted
according to Table 21.
Hardware interrupts are reported on the open-drain IRQ
pin. When an interrupt occurs, IRQ remains low until the
interrupt is serviced by reading the status register 0x00.
If a flag is set, it is reported as a hardware interrupt only
if the corresponding interrupt enable is set. Each bit
enables interrupts for the status flag in the respective
bit location in register 0x00. So IJDET must be set to
enable interrupts for jack detect.
Table 20. Jack-Detect Registers
Grayed boxes = Not used.
Table 21. Jack Sense (JKSNS)
Status
Jack Status
Interrupt Enable
Jack Detect
REGISTER
Jack Configuration Change Flag (JDET)
JKSNS[1:0]
Jack-Detect Interrupt Enable (IJDET)
JDETEN
00
01
10
11
______________________________________________________________________________________
ICLD
CLD
B7
JKSNS[1:0]
Headset Detection Overview
ISLD
SLD
B6
0
Mode Configuration
Jack Sense (JKSNS)
JDWK
IULK
ULK
JACKSNS is below V
JACKSNS is between V
Invalid.
JACKSNS is above V
B5
—
Low-Power, High-Performance
B4
Dual I
—
—
0
0
B3
—
0*
0
*
TH2
TH1
TH1
B2
and providing information to assist the system controller
in determining the configuration of an inserted plug. If
programmed to do so, upon insertion or removal of a
plug, the IRQ output is asserted (pulled low).
Table 20 shows the registers associated with the jack
detect function in MAX9880A.
Enables the jack-detect circuitry.
Enables a weak internal pullup current for reduced
power loss when the chip is in shutdown or the
MICBIAS is disabled.
JDWK = 0 enables a 2.2kΩ pullup to obtain full jack-
detect operation. This mode can be used to detect
insertion and removal of a plug as well as distinguish
between headphone and headset accessories.
JDWK = 1 enables a 4µA pullup current source when
SHDN = 0 or MICBIAS disabled. In this power-saving
configuration, the circuit can detect insertion and
removal of a plug but cannot distinguish between head-
phone and headset accessories.
The recommended usage follows: Set JDWK = 0 (or set
any bit in the microphone preamplifier gain registers
PALEN[1:0] or PAREN[1:0]). This enables the 2.2kΩ
pullup. Once the jack has been inserted and the type of
accessory determined, set JDWK = 1 to save power.
Once the plug is removed, set JDWK = 0.
—
0*
(low).
(high).
0
2
*
and V
S Stereo Audio Codec
IJDET
JDET
B1
—
TH2
DESCRIPTION
JDEB
(mid).
B0
—
—
0
Jack-Sense Weak Pullup (JDWK)
REGISTER
ADDRESS
Jack-Detect Enable (JDETEN)
0x00
0x01
0x04
0x25
POR STATE
0x00
0x00
—
—
R/W
R/W
R/W
R
R
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