MAX9880AEWM+T Maxim Integrated Products, MAX9880AEWM+T Datasheet - Page 30

• Manufacturer Part Number: MAX9880AEWM+T
• Description: CODECs Low-Power, High Perf ormance Dual I2S Ste
• Manufacturer: Maxim Integrated Products

Specifications of MAX9880AEWM+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Low-Power, High-Performance
Dual I
Hardware interrupts are reported on the open-drain IRQ
pin. When an interrupt occurs, IRQ remains low until the
interrupt is serviced by reading the status register 0x00.
Table 4. Interrupt Enable
The MAX9880A can work with a master clock (MCLK)
supplied from any system clock within the 10MHz to
60MHz range. Internally the MAX9880A requires a
10MHz to 20MHz clock. A prescaler divides MCLK by
1, 2, or 4 to create the internal clock (PCLK). PCLK is
used to clock all portions of the MAX9880A.
The MAX9880A can support any sample rate from 8kHz
to 48kHz for the digital audio path DAI1 (DAC and
ADC) and 8kHz to 96kHz for the DAI2 (high-fidelity
DAC path), including all common sample rates (8kHz,
16kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 96kHz). To
accommodate a wide range of system architectures,
the MAX9880A supports three main clocking modes:
• Normal mode: This mode uses a 15-bit clock
Table 5. System and Audio Clock Registers
* Reserved.
Grayed boxes = Not used.
Note: Register addresses listed are for I
accessible through SPI.
Grayed boxes = Not used.
Note: Register addresses listed are for I
accessible through SPI.
30
Interrupt Enable
SYSTEM CLOCK CONTROL
System Clock
DAI1 CLOCK CONTROL
Stereo Audio Clock Control High
Stereo Audio Clock Control Low
DAI2 CLOCK CONTROL
Stereo Audio Clock Control High
Stereo Audio Clock Control Low
divider coefficient to set the sample rate relative to
the prescaled MCLK input (PCLK). This allows high
______________________________________________________________________________________
REGISTER
REGISTER
2
S Stereo Audio Codec
ICLD
B7
Hardware Interrupts
PLL1
PLL2
B7
0
2
2
C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
ISLD
B6
Clock Control
B6
0
IULK
B5
B5
PSCLK
B4
NI1[7:1]
NI2[7:1]
0
B4
If a flag is set, it is reported as a hardware interrupt only
if the corresponding interrupt enable is set. Each bit
enables interrupts for the status flag in the respective
bit location in register 0x00.
• Exact integer mode: Common MCLK frequencies
• PLL mode: When operating in slave mode, a PLL
flexibility in both the MCLK and LRCLK frequencies
and can be used in either master or slave mode.
(12MHz, 13MHz, 16MHz, and 19.2MHz) can be pro-
grammed to operate in exact integer mode for both
8kHz and 16kHz sample rates. In these modes, the
MCLK and LRCLK rates are selected by using the
FREQ1 bits instead of the NI high, NI low, and PLL con-
trol bits.
can be enabled to lock onto externally generated
LRCLK signals that are not integer related to PCLK.
Prior to enabling the interface, program NI to the
nearest desired ratio and set the NI[0] = 1 to enable
the PLL’s rapid lock mode. If NI[0] = 0, then NI is
ignored and PLL lock time is slower.
B3
0*
NI1[14:8]
NI2[14:8]
B3
B2
0*
B2
FREQ1
IJDET
B1
B1
RLK1/NI1[0]
RLK2/NI2[0]
B0
B0
0
(SEE NOTE)
REGISTER
ADDRESS
REGISTER
(SEE NOTE)
ADDRESS
0x04
0x0B
0x0C
0x05
0x06
0x07