DS33R11 Maxim Integrated Products, DS33R11 Datasheet - Page 228

• Manufacturer Part Number: DS33R11
• Description: Network Controller & Processor ICs Ethernet Mapper with Integrated T1-E1-J1
• Manufacturer: Maxim Integrated Products

Specifications of DS33R11

• Product: Framer
• Number Of Transceivers: 1
• Supply Voltage (max): 1.89 V, 3.465 V
• Supply Voltage (min): 1.71 V, 3.135 V
• Supply Current (max): 100 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 5: BOC Clear Event (BOCC). Set when 30 FDL bits occur without an abort sequence.
Bit 4: RFDL Abort Detect Event (RFDLAD). Set when eight consecutive 1s are received on the FDL.
Bit 3: RFDL Register Full Event (RFDLF). Set when the receive FDL buffer (TR.RFDL) fills to capacity.
Bit 2: TFDL Register Empty Event (TFDLE). Set when the transmit FDL buffer (TR.TFDL) empties.
Bit 1: Receive FDL Match Event (RMTCH). Set whenever the contents of the TR.RFDL register matches
TR.RFDLM1 or TR.RFDLM2.
Bit 0: Receive BOC Detector Change-of-State Event (RBOC). Set whenever the BOC detector sees a change of
state to a valid BOC. The setting of this bit prompts the user to read the TR.RFDL register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 5: BOC Clear Event (BOCC)
Bit 4: RFDL Abort Detect Event (RFDLAD)
Bit 3: RFDL Register Full Event (RFDLF)
Bit 2: TFDL Register Empty Event (TFDLE)
Bit 1: Receive FDL Match Event (RMTCH)
Bit 0: Receive BOC Detector Change-of-State Event (RBOC)
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
—
—
7
0
7
0
TR.SR8
Status Register 8
24h
TR.IMR8
Interrupt Mask Register 8
25h
—
—
6
0
6
0
BOCC
BOCC
5
0
5
0
RFDLAD
RFDLAD
228 of 344
0
0
4
4
RFDLF
RFDLF
3
0
3
0
TFDLE
TFDLE
2
0
2
0
RMTCH
RMTCH
1
0
1
0
RBOC
RBOC
0
0
0
0