DS33R11 Maxim Integrated Products, DS33R11 Datasheet - Page 159

• Manufacturer Part Number: DS33R11
• Description: Network Controller & Processor ICs Ethernet Mapper with Integrated T1-E1-J1
• Manufacturer: Maxim Integrated Products

Specifications of DS33R11

• Product: Framer
• Number Of Transceivers: 1
• Supply Voltage (max): 1.89 V, 3.465 V
• Supply Voltage (min): 1.71 V, 3.135 V
• Supply Current (max): 100 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

11.5.2 X.86 Registers
X.86 transmit and common registers are used to control the operation of the X.86 encoder and decoder.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: X.86 Encoding Decoding (X86ED) If this bit is set to 1, X.86 encoding and decoding is enabled for the
Transmit and Receive paths. The MAC Frame is encapsulated in the X.86 Frame for Transmit and the X.86
headers are checked for in the received data. If X.86 functionality is selected, the X.86 receiver byte boundary is
provided by the RBSYNC signal and the DS33R11 provides the transmit byte synchronization TBSYNC. No HDLC
encapsulation is performed.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 - 7: X86 Transmit Receive Address (X86TRA0-7) This is the address field for the X.86 transmitter and for
the receiver. The register default value is 0x04.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 - 7: X86 Transmit Receive Control (X86TRC0-7) This is the control field for the X.86 transmitter and
expected value for the receiver. The register is reset to 0x03
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 - 7: X86 Transmit Receive Address (TRSAPIH0-7) This is the address field for the X.86 transmitter and
expected for the receiver. The register is reset to 0xfe.
X86TRA7
X86TRC7
TRSAPIH7
7
0
7
0
7
0
7
1
-
X86TRC6
X86TRA6
TRSAPIH6
6
0
6
0
6
0
6
1
-
LI.TX86EDE
X.86 Encoding Decoding Enable
0D8h
LI.TRX86A
Transmit Receive X.86 Address
0D9h
LI.TRX8C
Transmit Receive X.86 Control
0DAh
LI.TRX86SAPIH
Transmit Receive X.86 SAPIH
0DBh
X86TRC5
X86TRA5
TRSAPIH5
5
0
5
0
5
0
5
1
-
X86TRA4
X86TRC4
TRSAPIH4
159 of 344
0
0
0
1
4
4
4
4
-
X86TRC3
X86TRA3
TRSAPIH3
3
0
3
0
3
0
3
1
-
X86TRA2
X86TRC2
TRSAPIH2
2
0
2
1
2
0
2
1
-
X86TRC1
X86TRA1
TRSAPIH1
1
0
1
0
1
1
1
1
-
X86TRC0
X86TRA0
TRSAPIH0
X86ED
0
0
0
0
0
1
0
0