LAN91C110-PU SMSC, LAN91C110-PU Datasheet - Page 8

• Manufacturer Part Number: LAN91C110-PU
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C110-PU

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SMSC LAN91C110 Rev. B
75,72,80, 82-
83,81, 77,74-
73, 71-70,67
24,44,58, 68
18,19,21, 22 Transmit
144 TQFP
56-57, 60-
65, 46-48,
50-54, 35-
38, 40-42,
45, 25-28,
30-32, 34
86,84,85,
PIN NO.
16-13
139
141
140
137
78
23
12
11
10
2
3
1
8
6
RAM Data
Bus
RAM
Address
Bus
Crystal 1
Crystal 2
nLink
Status
AUI Select AUISEL
Transmit
Enable
MII
Carrier
Sense MII
Receive
Data Valid
Collision
Detect MII
Data
Transmit
Clock
Receive
Clock
Receive
Data
Manage-
ment Data
Input
Manage-
ment Data
Output
Manage-
ment
Clock
NAME
RD[31:0]
RA[16:2]
nROE
nRWE[3:0]
XTAL1
XTAL2
nLNK
TXEN100
CRS100
RX_DV
COL100
TXD[3:0]
TX25
RX25
RXD[3:0]
MDI
MDO
MCLK
SYMBOL
I with pullup Input. General purpose input port used to convey
I with pullup Input. Transmit clock input from MII. Nibble rate
I with pullup Input. Receive clock input from MII PHY. Nibble
BUFFER
I/O4 with
pulldown
pulldown
pulldown
pulldown
pullups
DATASHEET
TYPE
I with
I with
I with
I with
O12
O12
Iclk
O4
O4
O4
O4
O4
O4
I
Page 8
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
Bidirectional. Carries the local buffer memory
read and write data. Reads are always 32 bits
wide. Writes are controlled individually at the byte
level.
Outputs. This bus specifies the buffer RAM
doubleword being accessed by the LAN91C110.
Output. Active low signal used to read a
doubleword from buffer RAM.
Outputs. Active low signals used to write any
byte, word or dword in RAM.
An external 25 MHz crystal is connected across
these pins. If a TTL clock is supplied instead, it
should be connected to XTAL1 and XTAL2 should
be left open.
LINK status (EPHSR bit 14).
Output. Non volatile output pin. Driven by AUI
SELECT (CONFIG bit 8).
Output to MII PHY. Envelope to 100 Mbps
transmission.
Input from MII PHY. Envelope of packet reception
used for deferral and backoff purposes.
Input from MII PHY. Envelope of data valid
reception. Used for receive data framing.
Input from MII PHY. Collision detection input.
Outputs. Transmit Data nibble to MII PHY.
clock (25 MHz).
rate clock.
Inputs. Received Data nibble from MII PHY.
MII management data input.
MII management data output.
MII management clock.
DESCRIPTION
Revision 1.0 (11-04-08)
Datasheet