LAN91C110-PU SMSC, LAN91C110-PU Datasheet - Page 31

• Manufacturer Part Number: LAN91C110-PU
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C110-PU

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DATA REGISTER - Used to read or write the data buffer byte/word presently addressed by the pointer register.
This register is mapped into two uni-directional FIFOs that allow moving words to and from the LAN91C110 regardless of
whether the pointer address is even, odd or dword aligned. Data goes through the write FIFO into memory, and is pre-
fetched from memory into the read FIFO. If byte accesses are used, the appropriate (next) byte can be accessed through
the Data Low or Data High registers. The order to and from the FIFO is preserved. Byte word accesses can be mixed on
the fly in any order.
This register is mapped into two consecutive word locations. The DATA register is accessible at any address in the 8
through Ah range, while the number of bytes being transferred is determined by A1 and nBE0-nBE. The FIFOs are 12
bytes each.
BANK 2
This register can be read and written as a word or as two individual bytes.
The Interrupt Mask Register bits enable the appropriate bits when high and disable them when low. A MASK bit being set
will cause a hardware interrupt.
Note : The Bit 7 mask must never be written high (1).
SMSC LAN91C110 Rev. B
OFFSET
OFFSET
OFFSET
0
0
C
C
D
Reserved
Reserved
Reserved
0
0
INTERRUPT STATUS REGISTER
INTERRUPT ACKNOWLEDGE
INTERRUPT MASK REGISTER
EPH INT
EPH INT
MASK
0
REGISTER
0
NAME
NAME
NAME
RX_OVRN
RX_OVRN
RX_OVRN
MASK
DATASHEET
INT
INT
INT
0
0
Page 31
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
ALLOC
ALLOC
MASK
INT
INT
0
0
READ/WRITE
READ ONLY
WRITE ONLY
TYPE
TYPE
TYPE
EMPTY
EMPTY
EMPTY
MASK
INT
INT
INT
TX
TX
TX
1
0
TX INT
TX INT
TX INT
MASK
0
0
SYMBOL
SYMBOL
SYMBOL
ACK
MSK
IST
Revision 1.0 (11-04-08)
RCV INT
RCV INT
MASK
0
0
Datasheet