LAN91C110-PU SMSC, LAN91C110-PU Datasheet - Page 20

• Manufacturer Part Number: LAN91C110-PU
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C110-PU

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BANK 0
This register stores the status of the last transmitted frame.
completion, is stored as the first word in the memory area allocated to the packet. Packet interrupt processing should use
the copy in memory as the register itself will be updated by subsequent packet transmissions. The register can be used
for real time values (like TXENA and LINK OK). If TXENA is cleared the register holds the last packet completion status.
LINK_OK - General purpose input port driven by nLNK pin inverted. Typically used for Link Test. A transition on the value
of this bit generates an interrupt.
CTR_ROL - Counter Roll Over. When set one or more 4 bit counters have reached maximum count (15). Cleared by
reading the ECR register.
EXC_DEF - Excessive Deferral. When set last/ current transmit was deferred for more than 1518 * 2 byte times. Cleared
at the end of every packet sent.
LATCOL - Late collision detected on last transmit frame. If set a late collision was detected (later than 64 byte times into
the frame). When detected the transmitter jams and turns itself off clearing the TXENA bit in TCR. Cleared by setting
TXENA in TCR.
TX_DEFR - Transmit Deferred. When set, carrier was detected during the first 6.4 μs of the inter frame gap. Cleared at
the end of every packet sent.
LTX_BRD - Last transmit frame was a broadcast. Set if frame was broadcast. Cleared at the start of every transmit
frame.
SQET - Signal Quality Error Test. SQET bit is always set after first transmit, except if SWFDUP=1. As a consequence,
the STP_SQET bit in the TCR register cannot be set as it will always result in transmit fatal error. Transmission stops and
EPH INT is set if STP_SQET is in the TCR is also set when SQET is set. This bit is cleared by setting TXENA high.
16COL - 16 collisions reached. Set when 16 collisions are detected for a transmit frame. TXENA bit in TCR is reset.
Cleared when TXENA is set high.
LTX_MULT - Last transmit frame was a multicast. Set if frame was a multicast. Cleared at the start of every transmit
frame.
MULCOL - Multiple collision detected for the last transmit frame. Set when more than one collision was experienced.
Cleared when TX_SUC is high at the end of the packet being sent.
SMSC LAN91C110 Rev. B
BYTE
BYTE
HIGH
LOW
OFFSET
2
Reserved
DEFR
TX
0
0
EPH STATUS REGISTER
LINK_
-nLNK
BRD
LTX
OK
pin
0
NAME
Reserved
SQET
DATASHEET
0
0
16COL
_ROL
CTR
Page 20
0
0
READ ONLY
This register value, upon individual transmit packet
MULT
_DEF
EXC
LTX
TYPE
0
0
Reserved
MUL
COL
0
0
LATCOL
SNGL
SYMBOL
COL
EPHSR
0
0
Revision 1.0 (11-04-08)
Reserved
TX_SUC
0
0