LAN91C110-PU SMSC, LAN91C110-PU Datasheet - Page 38

• Manufacturer Part Number: LAN91C110-PU
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C110-PU

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.3
SMSC LAN91C110 Rev. B
1 ISSUE ALLOCATE MEMORY FOR TX - N
2 WAIT FOR SUCCESSFUL COMPLETION
3 LOAD TRANSMIT DATA - Copy the TX packet
4 ISSUE "ENQUEUE PACKET NUMBER TO TX
5
6
7
8 a) SERVICE INTERRUPT – Read Interrupt
packet number command to free up the memory
used by this packet. Remove packet number
from completion FIFO by writing TX INT
Acknowledge Register.
b) Option 1) Release the packet.
STATUS Register, write the packet number of
the current packet to the Packet Number
Register, re-enable TXENA, then go to step 4 to
start the TX sequence again.
BYTES - the MMU attempts to allocate N bytes
of RAM.
CODE - Poll until the ALLOC INT bit is set or
enable its mask bit and wait for the interrupt.
The TX packet number is now at the Allocation
Result Register.
number into the Packet Number Register. Write
the Pointer Register, then use a block move
operation from the upper layer transmit queue
into the Data Register.
FIFO" - This command writes the number
present in the Packet Number Register into the
TX FIFO. The transmission is now enqueued.
No further CPU intervention is needed until a
transmit interrupt is generated.
Status Register, exit the interrupt service
routine.
b) Option 1) Release the packet.
Typical Flow of Events for Transmit (Auto Release = 1)
Option 2) Check the transmit status in the EPH
S/W DRIVER
S/W DRIVER
DATASHEET
Page 38
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
a) The MAC generates a TXEMPTY interrupt
upon a completion of a sequence of enqueued
packets.
b) If a TX failure occurs on any packets, TX INT
is generated and TXENA is cleared, transmission
sequence stops. The packet number of the
failure packet is presented at the TX FIFO
PORTS Register.
The enqueued packet will be transferred to the
MAC block as a function of TXENA (nTCR) bit
and of the deferral process (1/2 duplex mode
only) state.
Transmit pages are released by transmit
completion.
MAC SIDE
MAC SIDE
Revision 1.0 (11-04-08)
Datasheet