FDMS9620S Fairchild Semiconductor, FDMS9620S Datasheet
FDMS9620S
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FDMS9620S Summary of contents
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... R Thermal Resistance, Junction to Ambient θJA Package Marking and Ordering Information Device Marking Device FDMS9620S FDMS9620S ©2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D3 ® MOSFET General Description = 7.5A D This device includes two specialized MOSFETs in a unique dual = 6.5A D Power 56 package. Synchronous Buck power stage in terms of efficiency and PCB = 10A utilization ...
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... Turn-Off Delay Time d(off) t Fall Time f Q Total Gate Charge g Q Gate to Source Gate Charge gs Q Gate to Drain “Miller” Charge gd ©2007 Fairchild Semiconductor Corporation FDMS9620S Rev. 25°C unless otherwise noted J Test Conditions I = 250μ 1mA 250μA, referenced to 25°C ...
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... Reverse Recovery Charge rr Notes determined with the device mounted on a 1in θJA the user's board design. 2: Pulse Test: Pulse Width < 300μs, Duty cycle < 2.0%. ©2007 Fairchild Semiconductor Corporation FDMS9620S Rev. 25°C unless otherwise noted J Test Conditions 2.1A (Note 2) GS ...
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... Figure 3. Normalized On Resistance vs Junction Temperature 40 μ PULSE DURATION = 300 DUTY CYCLE = 2.0%MAX =125 GATE TO SOURCE VOLTAGE (V) GS Figure 5. Transfer Characteristics ©2007 Fairchild Semiconductor Corporation FDMS9620S Rev. 25°C unless otherwise noted J 2 4.5V 2 1.8 1 3.5V GS 1.4 μ 1.2 s 1.0 ...
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... V , DRAIN to SOURCE VOLTAGE (V) DS Figure 9. Forward Bias Safe Operating Area 2 1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 0.1 0. ©2007 Fairchild Semiconductor Corporation FDMS9620S Rev. 25°C unless otherwise noted J =10V V = 15V 20V 100 1ms 10ms 100ms 1s 10s DC 10 100 ...
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... Junction Temperature 60 PULSE DURATION = 300 DUTY CYCLE = 2.0%MAX =125 GATE TO SOURCE VOLTAGE (V) GS Figure 16. Transfer Characteristics ©2007 Fairchild Semiconductor Corporation FDMS9620S Rev. 4. 3.5V GS μ PULSE DURATION = 300 s DUTY CYCLE = 2.0%MAX 1.5 2.0 2.5 Figure 13. Normalized on-Resistance vs Drain 75 100 125 150 μ ...
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... Typical Characteristics 10A GATE CHARGE(nC) g Figure 18. Gate Charge Characteristics ©2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D3 =10V 15V 20V 2000 1000 100 f = 1MHz 0 DRAIN TO SOURCE VOLTAGE (V) DS Figure 19. Capacitance vs Drain to Source Voltage C iss C oss C rss 30 10 www.fairchildsemi.com ...
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... Dimensional Outline and Pad Layout ©2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D3 8 www.fairchildsemi.com ...
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... Product Status Advance Information Formative or In Design Preliminary First Production No Identification Needed Full Production Obsolete Not In Production ©2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D3 FPS™ PDP-SPM™ F-PFS™ Power-SPM™ ® FRFET PowerTrench SM Global Power Resource Programmable Active Droop™ ...