CS1D-IC102D Omron, CS1D-IC102D Datasheet - Page 57

• Manufacturer Part Number: CS1D-IC102D
• Description: CS1D Dual IO Control Unit
• Manufacturer: Omron

Specifications of CS1D-IC102D

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Specifications
2-1-3
22
Restrictions
on interrupts
(Duplex CPU
Systems only)
Restrictions
on I/O refresh
methods
(Duplex CPU
Systems only)
Restrictions
on CPU pro-
cessing
modes
(Duplex CPU
Systems only)
Restrictions
on back-
ground exe-
cution
(Duplex CPU
Systems only)
Accuracy of
timer instruc-
tions in
Duplex CPU
Systems
PV refresh-
ing in Duplex
CPU Sys-
tems during
timer instruc-
tions in
jumped pro-
gram sec-
tions or in
stopped block
program sec-
tion (Differ-
ences from
CS1-H.)
Clock function
in Duplex
CPU Systems
Control method
I/O control method
Programming
Item
Common Specifications other than Duplex Specifications
Item
The CS1D CPU Units for Duplex CPU Systems do not support any interrupt
functions.
Power OFF interrupt tasks, scheduled interrupt tasks, I/O interrupt tasks, and
external interrupt tasks cannot be used in either Duplex or Simplex Mode. Inter-
rupt control instructions (MSKS, MSKR, and CLI) are executed as NOPs.
No restrictions.
Cannot be used in
Duplex CPU Sys-
tems (disabled).
Only Normal Mode can be used in Duplex CPU Systems. Parallel Processing
Mode and Peripheral Servicing Priority Mode cannot be used.
Background execution of text string instructions, table data instructions, and data
shift instructions cannot be used in Duplex CPU Systems.
If a timer instruction is being executed when operation is switched from duplex to
simplex, the error in the timer in the first cycle after switching may exceed the
normal time. In this case, the timer accuracy will be as follows:
TIM, TIMX, TIMH(015), TIMHX(
TIMLX(553), MTIM(543), MTIMX(
TMHWX(817):
TMHH(540), TMHHX(552):
TIM, TIMX, TIMH(015), TIMHX(
TTIMX(555):
The timer PV is not refreshed when the timer instruction is jumped for JMP,
CJMP, or CJPN-JME. The PV will be refreshed for the entire period it was
jumped the next time it is executed (i.e., the next time it is not jumped). (With
CS1-H CPU Units, the PV for these timers were refreshed even when jumped.)
TIMW(813), TIMWX(816), TMHW(815), TMHWX(817):
When the input condition for BPRG is OFF, or when the block program is tempo-
rarily stopped by BPPS, the timer PV is not refreshed. (With the CS1-H CPU
Units, the PV for these timers were refreshed each cycle.)
Synchronized with active CPU Unit.
(10 ms + cycle time)
Stored program
Cyclic scan and immediate processing (by IORF only)
are both supported.
Ladder diagram
(10 ms + cycle time
Cyclic refreshing
Refreshing by I/O refresh instruction (IORF(097))
Refreshing by CPU Bus Unit immediate refresh instruction
(DLINK(226))
Immediate refresh option “!”
Immediate refresh option “!” will be not be used even if it is
specified.
(10 ms + cycle time)
551
551
Specifications
554
), TTIM(087), TTIMX(555), TIML(542),
), TMHH(540), TMHHX(552), TTIM(087),
), TIMW(813), TIMWX(816), TMHW(815),
Specifications
10 ms or less
20 ms or less
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3-1-7 Duplex CPU Sys-
tem Restrictions
Appendix E Precau-
tions in Replacing CS1-
H PLCs with CS1D
PLCs
3-1-7 Duplex CPU Sys-
tem Restrictions
Appendix E Precau-
tions in Replacing CS1-
H PLCs with CS1D
PLCs
Reference
Reference
Section 2-1