ADNS-2610 Avago Technologies US Inc., ADNS-2610 Datasheet - Page 10

• Manufacturer Part Number: ADNS-2610
• Description: SENSOR OPTICAL MOUSE 8-DIP
• Manufacturer: Avago Technologies US Inc.

Specifications of ADNS-2610

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 516-1843; ADNS-2610

Power-down Mode (PD) and Timing
ADNS-2610 can be placed in a power-down mode by
setting bit 6 in the configuration register via a serial I/O
port write operation. Note that while writing a “1” to bit
6 of the configuration register, all other bits must be writ-
ten with their original value in order to keep the current
configuration. After setting the configuration register,
wait at least 32 system clock cycles. To get the chip out
of the power-down mode, clear bit 6 in the configuration
register via a serial I/O port write operation. (CAUTION! In
power-down mode, the SPI timeout (t
SDIO
Figure 12. Power-down timing.
The address of the configuration register is 0000000.
Assume that the original content of the configuration
register is 0x00.
SDIO
Figure 1. Power-down configuration register writing operation.
Setting the power down bit simply sets the analog circuitry
into a no current state.
Note: LED_CNTL, and SDIO will be tri-stated during power
down mode.
CLK
I DD
10
SCK
SCK
Operation
Write
1
1
0
A
6
0
Configuration Register Address
A
5
0
A
4
0
A
3
SPTT
0
) will not func-
D
0
5
D
0
4
D
3
0
D
2
1
Configuration Register Data
D
1
tion. Therefore, no partial SPI command should be sent.
Otherwise, the sensor may go into a hang-up state). While
the sensor is in power-down mode, only the bit 6 data will
be written to the configuration register. Writing the other
configuration register values will not have any effect. For
an accurate report after power-up, wait for a total period
of 50 ms before the microcontroller is able to issue any
write/read operation to the ADNS-2610. The sensor register
settings, prior to power-down mode, will remain during
power-down mode.
0
D
0
0
32 clock cycles min
0
t
PD
0
0
0