CYII4SM014KAA-GEC Cypress Semiconductor Corp, CYII4SM014KAA-GEC Datasheet - Page 9

• Manufacturer Part Number: CYII4SM014KAA-GEC
• Description: SENSOR IMAGE MONO CMOS 49-PGA
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII4SM014KAA-GEC

• Package / Case: 49-PGA
• Pixel Size: 8µm x 8µm
• Active Pixel Array: 3048H x 4560V
• Frames Per Second: 3
• Voltage - Supply: 3.3V
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: 0 C
• Image Size: 4560 H x 3048 V
• Color Sensing: Monochrome
• Package: 49PGA
• Operating Temperature: 0 to 50 °C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: IBIS4-14000-M; IBIS4-14000-M

Document #: 38-05709 Rev. *C
Sensor Readout Timing Diagrams
Row Sequencer
The row sequencer controls pulses to be given at the start of
each new line.
for this sequence.
The signals to be controlled at each row are:
• CLK_YL and CLK_YR: These are the clocks of the YL and
• SELECT: This signal connects the pixels of the currently
• PC: An initialization pulse that needs to be given to
• SHS (Sample & Hold pixel Signal): This signal controls the
• RESET: This pulse resets the pixels of the row that is
YR shift register. They can be driven by the same signals
and at a continuous frequency. At every rising edge, a new
row is being selected.
sampled line with the columns. It is important that PC and
SELECT are never active together.
precharge the column.
track & hold circuits in the column amplifiers. It is used to
sample the pixel signal in the columns. (0 = track ; 1 = hold)
currently being selected. In rolling shutter mode, the RESET
signal is pulsed a second time to reset the row selected by
the YR shift register. For “reset black” dark reference
signals, the reset pulse can be pulsed also during the first
PC pulse. Normally, the rising edge of RESET and the falling
Figure 10 on page 10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
shows the timing diagram
Figure 9. F Subsample Mode
m ode F - 1:12
Figure 10
image sensor and
the clocking scheme
• SHR (Sample & Hold pixel Reset level): this signal controls
• SYL (Select YL register): Selects the YL shift register to
• SYR (Select YR register): Selects the YR shift register to
• SYNC_YR and SYNC_YL: Synchronization pulse for the
• SYNC_X: Resets the column pointer to the first row. This
edge of PC occur at the same position. The falling edge of
RESET lags behind the rising PC edge.
another track & hold circuit in the column amplifiers. It is
used to sample the pixel reset level in the columns (for
double sampling). (0 = track ; 1 = hold)
drive the reset line of the pixel array
drive the reset line of the pixel array. For rolling shutter appli-
cations, SYL and SYR are complementary. In full frame
readout, both registers may be selected together, only if it
is guaranteed that both shift registers point to the same row.
This can reduce the row blanking time.
YR and YL shift registers. The SYNC_YR/SYNC_YL signal
is clocked in during a rising edge on CLK_YR/CLK_YL and
resets the YR/YL shift register to the first row. Both pulses
are pulsed only once each frame. The exact pulsing scheme
depends on the mode of use (full frame/ rolling shutter). A
200 ns set-up time applies. See
has to be done before the end of the first PC pulse, in case
when the previous line has not been read out completely.
shows the basic timing diagram of the IBIS4-14000
Table 4
CYII4SM014KAA-GEC
CYII4SC014KAA-GTC
shows the timing specifications of
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
Table 4 on page
Page 9 of 27
10.