CYII4SM014KAA-GEC Cypress Semiconductor Corp, CYII4SM014KAA-GEC Datasheet - Page 10

• Manufacturer Part Number: CYII4SM014KAA-GEC
• Description: SENSOR IMAGE MONO CMOS 49-PGA
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII4SM014KAA-GEC

• Package / Case: 49-PGA
• Pixel Size: 8µm x 8µm
• Active Pixel Array: 3048H x 4560V
• Frames Per Second: 3
• Voltage - Supply: 3.3V
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: 0 C
• Image Size: 4560 H x 3048 V
• Color Sensing: Monochrome
• Package: 49PGA
• Operating Temperature: 0 to 50 °C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: IBIS4-14000-M; IBIS4-14000-M

Document #: 38-05709 Rev. *C
Table 4. Timing Constraints for the Row Sequencer
Notes:
CLK = one clock period of the master clock, shortest system
time period available.
In the above timing diagram, the YR shift register is used for
the electronic shutter. The CLK_YR is driven identically as
Symbol
m
a
b
c
d
e
g
h
k
f
i
j
l
CLOCK_YL
SYNC_YR
SYNC_YL
SELECT
RESET
SHR
SHS
SYR
SYL
PC
h+2*CLK
200 ns
Min.
a
k
Optional reset pulse
l
1.28 µs
for reset black
600 ns
100 ns
500 ns
240 ns
2.7 µs
1.3 µs
6.5 µs
1.4 µs
500ns
10 µs
Typ.
5 µs
3µs
h
b
d
c
Min. SYNC set-up times. SYNC_Y is clocked in on rising edge on CLK_Y. SYNC_Y pulse
must overlap CLK_Y by one clock period. Set-up times of 200 ns apply after SYNC edges.
Within this set-up time no rising CLK edge may occur
Duration of PC pulse
Delay between falling edge on PC and rising edge on SHS/SHR. Duration of SHS/SHR
pulse
Delay between rising edge on PC and rising edge on SELECT
Delay between rising edge on SELECT and rising edge on SHS/SHR.
Delay between rising edge on SHS and falling edge on SELECT.
Delay between falling edge of SELECT and rising edge of RESET
Duration of RESET pulse
Delay between rising edge on SHR and rising edge on SYR
SYL and SYR pulses must overlap second RESET pulse at both sides by one clock cycle
Duration of CLOCK_Y pulse
Delay between falling edge of CLK_Y and Falling edge of PC and SHS
Delay between falling edge of RESET and falling edge of PC and SHR
e
f
Figure 10. Line Readout Timing
g
h
m
b
CLK_YL. The SYNC_YR pulse leads the SYNC_YL pulse by
a given number of rows. Relative to the row timing, both SYNC
pulses are given at the same time position.
SYNC_YR and SYNC_YL are only pulsed once each frame,
SYNC_YL is pulsed when the first row will be read out and
c
d
e
Description
f
i
Only when the electronic
j
shutter is used
CYII4SM014KAA-GEC
CYII4SC014KAA-GTC
h
j
Once each
For each
new row
frame
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