CYII4SM014KAA-GEC Cypress Semiconductor Corp, CYII4SM014KAA-GEC Datasheet
CYII4SM014KAA-GEC
Specifications of CYII4SM014KAA-GEC
IBIS4-14000-M
Related parts for CYII4SM014KAA-GEC
CYII4SM014KAA-GEC Summary of contents
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... This data sheet allows the user to develop a camera system based on the described timing and interfacing. Applications • Digital photography Typical Value • Document scanning • Biometrics 2 /W.s • 198 Champion Court • CYII4SC014KAA-GTC CYII4SM014KAA-GEC , San Jose CA 95134-1709 • Revised January 8, 2007 2 408-943-2600 ...
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... The shift registers can be configured for various subsampling modes. The output amplifiers can be individually powered down. And some other extra functions are foreseen. These options are configurable via a serial input port. CYII4SC014KAA-GTC CYII4SM014KAA-GEC CLK_YR SYNC_YR 4 parallel analog outputs Figure 2 on page 3) ...
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... SKY -------------- 4 analog outputs Pixel Specifications Architecture RESET Document #: 38-05709 Rev. *C Top of camera 3024 x 4536 active pixels 3048 x 4560 total pixels Figure 3. Pixel and Column Structure Schematic VDD_ARRAY M1 SELECT M2 CYII4SC014KAA-GTC CYII4SM014KAA-GEC 3024 x 24 dummy pixels Column PC M3 SHS SHR pixel 0,0 Page ...
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... Power control: the output amplifiers can be switched between an “operating” mode and a “standby” mode via the serial port of the imager (see the configuration). Figure 5. Color Filter Response Curve CYII4SC014KAA-GTC CYII4SM014KAA-GEC “Cover Glass” on page 24 for response “SPI Register ” on page 13 Page for ...
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... CLK_Y clock. Separate pins are used for the SYNC_Y and CLK_Y signals on the crossbar logic these pins can be connected to the SYNC_YL and CLK_YL pins of the shift register that is used for readout. Document #: 38-05709 Rev. *C CYII4SC014KAA-GTC CYII4SM014KAA-GEC . Figure 6. Output Amplifier Crossbar Switch CLK_YR Manual SYNC_YR ...
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... The row blanking time (dead time between readout of successive rows) has been set to 17.5 s. Image Resolution Frame rate [frames/s] 3024 x 4536 756 x 1134 378 x 567 252 x 378 Figure 2 on page CYII4SC014KAA-GTC CYII4SM014KAA-GEC Table 2. Use Use Frame readout time [s] 3.25 12.99 41.30 77.13 3). ...
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... Document #: 38-05709 Rev. *C Figure 7. B and C Subsample Mode mode B - 1:1 mode C - 1:4 CYII4SC014KAA-GTC CYII4SM014KAA-GEC Page ...
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... Document #: 38-05709 Rev. *C Figure 8. D and E Subsample Mode m ode D - 1:6 m ode E - 1:8 CYII4SC014KAA-GTC CYII4SM014KAA-GEC Page ...
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... See • SYNC_X: Resets the column pointer to the first row. This has to be done before the end of the first PC pulse, in case when the previous line has not been read out completely. Figure 10 image sensor and the clocking scheme CYII4SC014KAA-GTC CYII4SM014KAA-GEC ...
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... CLK_YL. The SYNC_YR pulse leads the SYNC_YL pulse by a given number of rows. Relative to the row timing, both SYNC pulses are given at the same time position. SYNC_YR and SYNC_YL are only pulsed once each frame, SYNC_YL is pulsed when the first row will be read out and CYII4SC014KAA-GTC CYII4SM014KAA-GEC ...
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... SHR can be kept high since they don’t interact with the pixel reset mechanism. Table 5 on page 12 CLK_Y and SELECT. Figure 11. Row Readout Timing Sequence ixe CYII4SC014KAA-GTC CYII4SM014KAA-GEC shows the reset timing for a fast frame lists timing specifications for RESET, p ixe ixe l 3 Page ...
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... Reset hold time. 1.6 µs d Select pulse width. 1 µs e Setup hold time. CONSTRAINT > due to propagation delay on pixel select line. CLK_YR CLK_YL SELECT PC SHS RESET SHR SYL SYR SYNC_YR SYNC_YL Document #: 38-05709 Rev. *C Description Figure 12. Fast Reset Sequence Timing CYII4SC014KAA-GTC CYII4SM014KAA-GEC Page ...
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... The code is uploaded serially as a 16-bit word (LSB uploaded first). Table 7 on page 14 code for a full resolution readout is 33342 (decimal) or 1000 0010 0011 1110. CYII4SC014KAA-GTC CYII4SM014KAA-GEC 16 outputs to sensor core Tsclk D1 D2 D15 lists the register definition. The default Figure 13 ...
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... CS: chip select, a rising edge on CS loads the parallelized data into the on-chip register. The initial state of the register is undefined. However, no state exists that destroys the device. CYII4SC014KAA-GTC CYII4SM014KAA-GEC Page ...
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... Low active. Synchronous sync on rising edge of CLK_YL 200 ns set-up time. High active. Exact pulsing pattern see timing diagram. Both SYR = 1 and SYL = 1 is not allowed, except when the same row is selected. CYII4SC014KAA-GTC CYII4SM014KAA-GEC shows the assignment of pin numbers Comment Page ...
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... Low active. Synchronous sync on rising edge of CLK_X 150 ns set-up time. 0V Nominal 3.3V Shifts on rising edge. See timing diagram. See timing diagram. Connect with 10 kΩ to VDD and decouple with 100 nF to GND. Connect with 10 MΩ to VDD and decouple with 100 nF to GND. CYII4SC014KAA-GTC CYII4SM014KAA-GEC Comment Page ...
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... Vsat RMS Average value of RMS variation on local pixel windows. 0.15% Vsat RMS <1% RMS of signal 5 10 Charge spill-over to neighboring pixels (= CCD blooming mechanism) CYII4SC014KAA-GTC CYII4SM014KAA-GEC Remarks 13.9 megapixels 20 MHz with extra power dissipation. Full resolution with 4 parallel analog outputs @ 15 MHz/channel Remarks Page ...
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... Spectral Response Curve Electro-voltaic Response Curve Document #: 38-05709 Rev. *C Figure 14. IBIS4-14000 Spectral Response Curve Figure 15. IBIS4-14000 Electro-voltaic Response Curve CYII4SC014KAA-GTC CYII4SM014KAA-GEC Page ...
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... Tolerance on bias reference voltages: ±150 mV due to process variances. Document #: 38-05709 Rev. *C Description Description [2] Connection 10k to VDD 22k to VDD 22k to VDD 10k to VDD or 10M to VDD CYII4SC014KAA-GTC CYII4SM014KAA-GEC Value –0.5 to +4.5 –0 0.5 DC –0 0.5 DC ±50 – 15% RH) –10 to +38 (@ 86% RH) (RH = relative humidity) 8000 Min ...
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... Document #: 38-05709 Rev. *C Figure 16. Die Geometry and Location of Pixel (0,0) to package ground plane) Locations of temperature sensing diodes Location of photodiode array CYII4SC014KAA-GTC CYII4SM014KAA-GEC pixel 0,0 Ground pad, also connected to package ground plane Analog output pad Ground for output pad (not connected Page ...
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... Pin Number Assignment Note: “Solid” drawn pins are connected to die attach area for a proper ground plane Document #: 38-05709 Rev. *C Figure 17. Pin Number Assignment Package Back side CYII4SC014KAA-GTC CYII4SM014KAA-GEC Page ...
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... Package Drawings all dimensions in mm Document #: 38-05709 Rev. *C Figure 18. Package Dimensions CYII4SC014KAA-GTC CYII4SM014KAA-GEC Page ...
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... Die Placement Dimensions and Accuracy 200 2 all dimensions in mm Document #: 38-05709 Rev. *C Figure 19. Die Placement Figure 20. Tolerances CYII4SC014KAA-GTC CYII4SM014KAA-GEC Page ...
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... Document #: 38-05709 Rev. *C Figure 21. D-263 Transmittance Curve 500 600 Wavelength [nm] Figure 22. S8612 Transmittance Curve (w/o AR coating) 500 600 700 Wavelength [nm] • Substrate: Schott S8612 glass • Thickness: 0.7 mm ±0.050 mm • Size: 31.9 x 44.9 mm CYII4SC014KAA-GTC CYII4SM014KAA-GEC 700 800 800 900 1000 2 ±0.2 mm 900 Page ...
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... Avoid mechanical stress when mounting the device. RoHS (lead-free) Compliance This paragraph reports the use of Hazardous chemical substances as required by the RoHS Directive (excluding packing material). Any intentional content CYII4SC014KAA-GTC CYII4SM014KAA-GEC teristics or cause a scar. In order to If there is any intentional content, in which portion is it contained Page ...
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... Information on lead free soldering CYII4SM014KAA-GEC: the product was tested successfully for lead-free soldering processes, using a reflow temperature profile with maximum 260°C, minimum 40s at 255°C and minimum 90s at 217°C. CYII4SC014KAA-GTC: the product will not withstand a lead-free soldering process. Maximum allowed reflow or wave soldering temperature is 220° ...
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... Orig. of Change See ECN SIL See ECN FVK See ECN FVK See ECN FPW CYII4SC014KAA-GTC CYII4SM014KAA-GEC Description of Change Initial Cypress release Layout converted Figure 10 on page 10 updated Storage and handling section added IBIS4-14000-C added Updated MPN Ordering information update+package spec label. ...