CYII4SM014KAA-GEC Cypress Semiconductor Corp, CYII4SM014KAA-GEC Datasheet - Page 13

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CYII4SM014KAA-GEC

Manufacturer Part Number
CYII4SM014KAA-GEC
Description
SENSOR IMAGE MONO CMOS 49-PGA
Manufacturer
Cypress Semiconductor Corp
Type
CMOS Imagingr

Specifications of CYII4SM014KAA-GEC

Package / Case
49-PGA
Pixel Size
8µm x 8µm
Active Pixel Array
3048H x 4560V
Frames Per Second
3
Voltage - Supply
3.3V
Operating Supply Voltage
3.6 V
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
0 C
Image Size
4560 H x 3048 V
Color Sensing
Monochrome
Package
49PGA
Operating Temperature
0 to 50 °C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
IBIS4-14000-M
IBIS4-14000-M
Document #: 38-05709 Rev. *C
SPI Register
SPI Interface Architecture
The elementary unit cell of the serial to parallel interface consists of two D-flip-flops. The architecture is shown in
of these cells are connected in parallel, having a common /CS and SCLK form the entire uploadable parameter block, where D
is connected to D
Table 6. Timing Requirements Serial-Parallel Interface
SPI Register Definition
Sensor parameters can be serially uploaded inside the sensor
at the start of a frame. The parameters are:
• Subsampling modes for X and Y shift registers (3-bit code
• Power control of the output amplifiers, column amps and
for 6 subsampling modes)
pixel array. Each amplifier can be individually powered
up/down
Parameter
CS
Din
SCLK
Tsclk
Th
Ts
out
Unity Cell
of the next cell. The uploaded settings are applied to the sensor on the rising edge of signal /CS.
D
D
C
C
To sensor core
Q
Q
Dout
100 ns
Value
50 ns
50 ns
SCLK
Din
Figure 13. SPI Interface
Data
valid
SCLK
Din
CS
CS
The code is uploaded serially as a 16-bit word (LSB uploaded
first).
Table 7 on page 14
code for a full resolution readout is 33342 (decimal) or 1000
0010 0011 1110.
D0
• Output crossbar switch control bits. The crossbar switch is
used to route the green pixels to the same output amplifiers
at all time. A first bit controls the crossbar. When a second
bit is set, the first bit will toggle on every CLK_Y edge in
order to automatically route the green pixels of the bayer
filter pattern.
Entire uploadable parameter block
16 outputs to sensor core
D1
Tsclk
D2
lists the register definition. The default
CYII4SM014KAA-GEC
CYII4SC014KAA-GTC
D15
Ts
Page 13 of 27
Th
Figure
Dout
13. 16
in

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